Fall 2014: Upcoming Seminars

  • Title: [SSCS Distinguished Lecture] The Return of Neuro-Inspired Computing - Why Now?
          Speaker: Prof. Jan M. Rabaey, UC-Berkeley
  •       Date: Friday, Nov 21st, 2:00pm-3:00pm, 750, CEPSR

    Dr. Frank O'Mahony
    Intel, Hillsboro, Oregon

    Friday, Oct. 17th, 2:00pm-6:00pm
    833, MUDD

    [SSCS Distinguished Lecture Tour-1] On-Chip Voltage and Timing Diagnostic Circuits

    This talk introduces a set of practical and powerful techniques and circuits to observe and characterize on-die circuitry. Measuring voltage and timing information on the chip itself alleviates the bandwidth and noise limitations associated with bringing signals off-chip to be measured. Specific applications of these techniques include measurement and characterization of power supply noise, power delivery impedance, clock skew, phase interpolator linearity, I/O eye margins, waveform capture, RX voltage noise and hysteresis, and RX clock-data jitter. Because the measurements are fully integrated, the rest of the system can be automatically adapted based on these metrics in a stand-alone manner. Best of all, many of these techniques leverage existing circuitry and are highly digital.

    Frank currently leads the I/O Circuit Technology group within Advanced Design at Intel in Hillsboro, Oregon, where he is a Principal Engineer. His group develops the first wireline I/O circuits for each new CMOS process technology at Intel. From 2003 until 2011 he was a member of the Signaling Research group in Intel's Circuit Research Lab. His research interests include high-speed and low-power wireline transceivers, clock generation and distribution, equalization, analog circuit scaling, and on-die measurement techniques. Frank received the BS, MS, and PhD degrees in electrical engineering from Stanford University. Frank is a member of the ISSCC Wireline Subcommittee and previously served as an Associate Editor for TCAS-I. He is a past recipient of the ISSCC Jack Kilby Award and TCAS Darlington Best Paper Award.

    Prof. Payam Heydari

    Friday, Oct. 17th, 2:00pm-6:00pm
    833, MUDD

    [SSCS Distinguished Lecture Tour-2] Terahertz and Millimeter-Wave Frequency Generation and Synthesis in Silicon

    THz and millimeter-wave (mm-wave) imaging and sensing is considered to be one of the emerging and disruptive technologies over the next decade. THz (including the W-band) waves pass through non-conducting materials such as clothes, paper, wood and brick and so cameras sensitive to them can peer inside envelopes, into living rooms and "frisk" people at distance. THz/mm-wave imaging and sensing systems, therefore, will be key enabling components in applications such as security surveillance (to find concealed weapons and explosives), nondestructive testing, biology, radio astronomy, multi-gigabit wireless connectivity, and medical imaging. One of the most critical and daunting tasks in a THz/mm-wave system is signal generation and frequency synthesis. This invited talk presents an overview and comparative study of recent research efforts which have explored several circuit techniques and architectures leading to highly efficient frequency synthesis, signal generation, and mm-wave LO distribution networks in silicon.

    Payam Heydari received his B.S. and M.S. degrees (Honors) in Electrical Engineering from Sharif University of Technology in 1992 and 1995, respectively. He received his Ph.D. degree from the University of Southern California in 2001. He is currently a Professor of Electrical Engineering at the University of California, Irvine.
    His research covers the design of terahertz/millimeter-wave/RF/analog integrated circuits. He is the (co)-author of two books, one book chapter, and more than 110 journal and conference papers. He has given Keynote Speech to IEEE GlobalSIP 2013 Symposium on Millimeter Wave Imaging and Communications and served as Invited Distinguished Speaker to the 2014 IEEE Midwest Symp. on Circuits and Systems. He is the Distinguished Lecturer of IEEE Solid-State Circuits Society.
    Dr. Heydari is recipient of the Distinguished Engineering Educator Award from Orange County Engineering Council. He is the recipient of the 2010 Faculty of the Year Award from UC-Irvine's Engineering Student Council (ECS), the 2009 School of Engineering Best Faculty Research Award, the 2007 IEEE Circuits and Systems Society Guillemin-Cauer Award, the 2005 IEEE Circuits and Systems Society Darlington Award, the 2005 National Science Foundation (NSF) CAREER Award, the 2005 Henry Samueli School of Engineering Teaching Excellence Award, and the Best Paper Award at the 2000 IEEE Int'l Conference on Computer Design (ICCD). The Office of Technology Alliances at UCI has named Dr. Heydari one of 10 Outstanding Innovators at the university. He is the co-recipient of the 2009 Business Plan Competition First Place Prize Award and Best Concept Paper Award both from Paul Merage School of Business at UC-Irvine. He was recognized as the 2004 Outstanding Faculty in the EECS Department of the University of California, Irvine. His research on novel low-power multi-purpose multi-antenna RF front-ends received the Low-Power Design Contest Award at the 2008 IEEE Int'l Symposium on Low-Power Electronics and Design (ISLPED).
    Dr. Heydari currently serves on the Technical Program of International Solid-State Circuits Conference (ISSCC). He served as the Guest Editor of IEEE Journal of Solid-State Circuits (JSSC), and Associate Editor of IEEE Trans. on Circuits and Systems - I, and served on the Technical Program Committees of Compound Semiconductor IC Symposium (CSICS), Custom Integrated Circuits Conference (CICC), and ISLPED. He served on the Technical Program Committees of and Int'l Symposium on Quality Electronic Design (ISQED), IEEE Design and Test in Europe (DATE) and International Symposium on Physical Design (ISPD). He is the director of the Nanoscale Communication IC (NCIC) Labs.

    Prof. R. Jacob Baker
    Univ. of Nevada

    Friday, Oct. 17th, 2:00pm-6:00pm
    833, MUDD

    [SSCS Distinguished Lecture Tour-3] Low-Power, High-Bandwidth, and Ultra-Small Memory Module Design

    This work proposes a novel DRAM module and interconnect architectures in an attempt to improve computing energy use and performance. A low cost advanced packaging technology is used to propose an 8 die and 32-die memory module. The 32-die memory module measures less than 2 cm3. The size and packaging technique allow the memory module to consume less power than conventional module designs. A 4 Gb DRAM architecture utilizing 64 data pins is proposed. The DRAM architecture is inline with ITRS roadmaps and can consume 50% less power while increasing bandwidth by 100%. The largenumber of data pins are supported by a low power capacitive-coupled interconnect. The receivers developed for the capacitive interface were fabricated in 0.5 µm and 65 nm CMOS technologies. The 0.5 µm design operated at 200 Mbps, used a coupling capacitor of 100 fF, and consumed less than 3 pJ/bit of energy. The 65 nm design operated at 4 Gbps, used a coupling capacitor of 15 fF, and consumed less than 15 fJ/bit and order of magnitude smaller consumptions than previously reported receiver designs.

    R. Jacob Baker is a Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas. His research interests lie in integrated electrical/biological circuits and systems, interfacing CMOS to Silicon Photonics, and the delivery of online engineering education. He has extensive industry experience and is the author of several circuit design books. Additional information can be found at

    Prof. Mike Shuo-Wei Chen
    University of Southern California

    Friday, Oct. 24th, 1:00pm-2:00pm
    EE Conference Room, 1300 MUDD

    Rethinking Analog-Digital Interface Circuit Architectures

    The trend of modern electronic systems in both wireless and wireline applications demands increasing bandwidth, dynamic range, and reconfigurability but low power and cost. On the other hand, the technology scaling is slowing down its pace and incurs significant cost particularly for analog designs. Those factors have driven the mixed-signal design community to pursue new circuit architectures towards unprecedented performance, power efficiency and flexibility. In this talk, we will examine several such attempts in ADC, DAC, and PLL designs recently demonstrated by our group members. The initial silicon prototypes in 65nm CMOS achieve encouraging power efficiency and performance in comparison with the state of the arts, which tout the potential for many future extensions.

    Mike Shuo-Wei Chen received the B.S. degree from National Taiwan University in 1998, and the M.S. and Ph.D. degree from the University of California, Berkeley in 2002 and 2006, all in Electrical Engineering. Since 2006, he has been working on mixed-signal and RF circuits for various wireless standards at Atheros communications (now Qualcomm-Atheros). He joined EE department at University of Southern California since 2011. His research group is having fun with exploring the limit of analog mixed-signal, RF ICs, Bio-inspired electronics, and signal processing techniques for circuits and systems. Dr. Chen achieved an honourable mention in the Asian Pacific Mathematics Olympiad, 1994. He was the recipient of NSF Faculty Early Career Development (CAREER) Award, DARPA Young Faculty Award (YFA) in 2014, UC Regents’ Fellowship at Berkeley in 2000 and Analog Devices Outstanding Student Award for recognition in IC design in 2006.

    Prof. Jan M. Rabaey
    Donald O. Pederson Distinguished Professor, University of California at Berkeley

    Friday, Nov 21st, 2:00pm-3:00pm
    501, NWC

    [SSCS Distinguished Lecture] The Return of Neuro-Inspired Computing - Why Now?

    Barring technologies surprises (such as the discovery of a perfect nanometer switch), alternative design strategies may be necessary if continued scaling of functionality in terms of size and energy is to be obtained. Neuro-inspired computing is one possible direction to be considered. Over the past decade, the brain has been receiving a lot of attention (e.g. the BRAIN initiatives in the US and Europe)-mostly from a mapping and an understanding perspective. The brain is an amazingly complex and efficient machine. While it may not be considered "general purpose" in terms of its computational capabilities, it performs a set of functions such as feature extraction, classification, synthesis, recognition, learning, and higher-order decision-making amazingly well. Carver Mead already realized this in the late 1980's- yet the technological landscape at that time was not amenable to make neuromorphic computing an attractive alternative.
    Today, it is realized that neuro-inspired computing may be a perfect match to the properties of the emerging nano-scale devices (such as 3D integration, carbon and spin devices, non-volatile memory cells such as RRAM, etc): it thrives on randomness and variability, processing is performed in the continuous or discrete domains, and massive parallelism, major redundancy and adaptivity are of essence. Computational paradigms inspired by neural information processing hence may lead to energy-efficient, low-cost, dense and/or reliable implementations of the functions the brain excels at. In this presentation, we will explore various means on how the interaction between neuroscience and information technology may lead to an exciting future.

    Prof. Jan Rabaey is the founding director of the Berkeley Wireless Research Center and the Ubiquitous Swarm Lab. He has been on the forefront of many groundbreaking innovations in low-energy design, and is currently exploring the interaction between information technology and neuroscience.

    Fall 2014 Seminars

  • Title: [SSCS Distinguish lecture Tour] The Recent Advances in RF, Mixed-Signal and Digital IC designs
          Speaker: Dr. Frank O'Mahony, Intel
          Speaker: Prof. Payam Heydari, UC-Irvine
          Speaker: Prof. R. Jacob Baker, Univ. of Nevada
          Date: Friday, Oct 17th, 2:00pm-6:00pm, 833, MUDD

  • Title: Rethinking Analog-Digital Interface Circuit Architectures
          Speaker: Prof. Mike Shuo-Wei Chen
  •       Date: Friday, Oct 24st, 1:00pm-2:00pm, EE Conf. Room, 1300 MUDD

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