Seminars:
Prof. Georges Gielen
Katholieke Universiteit Leuven, Belgium
Date: Wednesday, September 7, 2005
Place: 414 CEPSR
Title:
Reconfigurable Front-End Architectures and A/D Converters for
Software-Defined Radios
Abstract:
Flexibility is a key feature in 4G telecom systems, where there is a demand for reconfigurable transceivers that can cope with multiple standards (cellular, WLAN, Bluetooth, etc.). Additionally, these transceivers should adapt to the environment (presence of received blockers or not, status of battery power levels, etc.) to minimize power consumption and optimize performance according to the needs of the customer and the desired Quality of Service. In addition, flexibility is required to cut the development time and cost to implement a new future standard into the 4G system. All this calls for a digitally controlled front-end architecture ("software-defined radio") with reconfigurable RF and analog baseband blocks controlled through digital programmable software. This poses serious challenges to the design of such reconfigurable yet power-efficient RF/analog blocks. For the analog-to-digital converters in the receiver, this comes down to designing a power- and area-efficient reconfigurable converter with variable bandwidth and dynamic range. The general requirements for such converters in 4G systems will be described. This will then be illustrated with the design of a reconfigurable continuous-time delta-sigma A/D converter with a pipelined multibit quantizer and 1-bit feedback. The chip has been realized in a 0.18 µm CMOS technology. It has 3 different modes (20 MHz BW/58dB SNDR, 4 MHz BW/60dB SNDR, 0.2MHz BW/70dB SNDR). The chip has an active area of 0.9 mm2 and the power consumption for the most demanding mode (20 MHz/58 dB) is 37 mW.
Prof. Donhee Ham
Harvard University
Date: Friday, October 7, 2005, 2:00pm
Place: Dept of EE, Conference room, 13th Floor, Mudd
Title: Soliton
Electronics and Biolab-on-Chip
Abstract:
This talk consists of two topics, that have been important research foci in my lab.
In the first part of this talk, I will present the first stable self-sustained electrical soliton oscillator that we have recently developed. The soliton oscillator consisting of a nonlinear transmission line (NLTL) and a nonlinear amplifier that "tames" the instability-prone dynamics of the NLTL self-starts by amplifying background noise to generate a stable soliton train in steady-state. While the NLTL has been extensively exploited as a sharp soliton pulse generator in the past decades, this traditional approach utilizes the NLTL as a 2-port system that requires an external high-frequency input to generate the soliton output. Our soliton oscillator is a self-contained 1-port system that does not require any external high-frequency input in generation of the soliton train. The soliton oscillator, as a direct analogue of the optical soliton mode-locked system such as the soliton fiber ring laser, is expected to find a variety of applications in high-speed metrology.
The second part of this talk covers a CMOS/microfluidic hybrid microsystem, which our group is developing as a new biolab-on-IC in collaboration with Westervelt group at Harvard. The hybrid system consists of a CMOS chip and a microfluidic system fabricated on top. A microcoil array circuit in the CMOS chip produces a spatially-patterned microscopic magnetic field pattern to simultaneously manipulate multiple individual biological cells (tagged by magnetic beads) suspended inside the microfluidic system. Fullying exploiting the programmability and speed of the CMOS chip, the manipulation operations are performed with low power and high spatial manipulation resolution. The hybrid system may be used as a micro cellular assembler.
Dr. Jack Kenney
Analog Devices Inc.
Date: Friday, December 2, 2005, 2:00pm
Place: 414 CEPSR
Title: Clock and
Data Recovery Circuit of 10Gbps Serial Data in 0.13um CMOS
Abstract:
Prior to the
introduction of 0.13um CMOS, circuits for 10Gbps serial
receivers were implemented in high-speed processes such as SiGe. CMOS
processes at channel lengths of 0.13um and smaller have sufficiently
fast core devices to process 10Gbps data streams. The architecture and
circuit design for a 10Gbps clock and data recovery circuit based upon
a half-rate binary phase detector using a delay interpolating VCO will
be described; the binary phase detector is the basis of a bang bang
phase-locked loop.
The talk will
begin with a tutorial overview of the operation and
jitter properties of a bang bang phase-locked. It will next delve into
the architecture for a half-rate binary phase detector and describe
some of the circuit challenges.
Biography:
Jack Kenney was
born in Springfield, MA. He received BS degrees from
both Providence College and Columbia University in 1984. His first
exposure to analog circuit design was at Motorola Corp. where he
developed analog front ends for voiceband telephone applications. Jack
received an MSECE and PhD from Carnegie Mellon University in 1988 and
1991 respectively. He was on the faculty of the Department of ECE at
Oregon State University from 1992 until 1997 where he achieved the rank
of Associate Professor. His other academic posts include Visiting
Researcher at the Data Storage Systems Center (DSSC) of the National
University of Singapore in Summer 1996, and Visiting Lecturer with the
Department of Electrical Engineering at Princeton University in Fall
1999. Jack is now employed by Analog Devices Inc. in Somerset, NJ,
where he spent 3 years developing CMOS analog integrated circuits for
the ADSL application and is currently designing clock and data recovery
circuits for 10Gbps fiber optic channels in 0.13um CMOS.
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