Prof. John McNeill
Worcester
Polytechnic Institute, Massachusetts
Date: 2:00pm, Friday, April 28, 2006
Place: 414 CEPSR
Title:
Deep Submicron CMOS and the New Era of Creativity in
Analog Design
Abstract:
Analog and mixed
signal IC designers frequently see themselves as
artists -- and like any artist, the analog designer uses whatever
style, medium, and tools that are best suited to the problem at
hand. Deep submicron CMOS is just another tool for the analog
designer to use. The capability for small inexpensive digital
circuitry is not a threat to analog design, but actually opens new
avenues for creativity. In this talk, the theme of "old" and "new"
analog CMOS design will be explored with examples drawn from mixed
signal circuit designs in the area of data conversion.
Mr. Benjamin
Van Camp
Director of custom
IC at Sarnoff Europe
Date: 2:00pm, Friday, April 7, 2006
Place: EE Conference Room 1312 S.W. Mudd
Title: ESD
for advanced CMOS nodes
Abstract:
Due to the
continuous scaling of the CMOS technology, Electro Static
Discharge (ESD) protection design is ever more challenging. Ultra thin
gate oxides and sensitive output drivers drastically reduce the
available voltage margin for the traditional protection approaches.
After a basic introduction on on-chip ESD protection, the tutorial
presents an overview of the different protection approaches and their
applicability for the emerging IC's and systems in advanced technology
nodes.
Dr. Venu
Gopinathan
Director, Wireless
Solutions Group
Texas Instruments,
Bangalore, India
Date: Monday, April 3, 2006
Place: 414 CEPSR
Title: Tuning of
Analog Parameters - A tutorial
Abstract:
Variability of
basic parameters like transconductances, time-constants
and gains due to process, voltage and temperature variations, can have
first-order effect in the performance and manufacturability of most
analog circuits. This tutorial focuses on negative feedback circuits
that can be implemented on-chip to combat these variations. A
discussion of pros and cons of various circuits that tune
time-constants (for continuous-time filters), gm's of transistors,
quality-factors of resonators etc. will be discussed.
Dr.
Phil Diodato
Agere Systems Inc.
Date: Friday, March 24, 2006
Place: EE Conference Room 1312 S.W. Mudd
Title: "RE:
Engineering in Reverse"
Abstract:
Competitive
analysis and patent portfolio security are important
activities in modern scientific corporations. Techniques for gathering
sub-micron scientific evidence intended for use in semiconductor patent
infringement cases are reviewed. Motivational comments geared for first
year college engineering students are included.
Prof. Francesco
Svelto
University of
Pavia, Italy
Date: Friday, February 3, 2006
Place: Interschool lab CEPSR
Title: Challenges
in
the RF design of highly integrated Direct Conversion Receivers for
multi-band, multi-standard applications
Abstract:
The demanding
dynamic range required by
receivers for wireless wide area networks still make the design of
low-power highly integrated CMOS solutions a topic of intense research.
This presentation starts discussing highly linear direct
down-converters and low-power quadrature generators, based on injection
locked dividers, tailored to fully integrated cell-phone receivers.
Getting rid of external components is even more important in
multi-standard applications, where several transceivers are likely to
coexist on the same PCB. Reconfigurable front-ends, based on a
voltage-voltage feedback LNA topology and the highly linear mixer, are
introduced. Implementation examples include a 0.13mm CMOS
DCS1800/UMTS/IEEE802.11b and g, and a 0.25mm BiCMOS 5-6GHz
multi-standard WLAN. Finally, the potentials of a multi-resonance
feedback LNA are exploited in a 0.18mm CMOS front-end for multi-band
OFDM UWB applications, operating in the 3.1GHz-8GHz frequency range.
|
