Seminars Spring 2004
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Robert H. Dennard
IBM T.J. Watson
Date: Thursday May 6, 2004, 2:30pm
Place: Interschool Lab (7th Floor), Schapiro Building
Title: Scaling Challenges and Future Trends in Microelectronics
Abstract:
Measures of the rate of progress in microelectronics, known as Moore's
law, have been very useful in prediction and future planning. This
progress can perhaps best be understood in terms of the concept of scaling
which was introduced by the speaker and coworkers in the early 1970's.
We have come to expect reduction of the transistor and wiring dimensions
at a regular pace, along with the critical gate oxide thickness which
makes transistor scaling work. Over the last thirty-five years these
dimensions have been reduced by a factor of about 80-100, leading to the
present situation where we are encountering basic barriers to further
scaling of dimensions. This presentation addresses whether and when this
progress will slow or cease and the microelectronics industry will mature.
Also, what will microelectronics be like in maturity and can it support
all our needs for computing?
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Tanay Karnik
Intel Corporation
Date: Friday April 30, 2004, 2:30pm
Place: Interschool Lab (7th Floor), Schapiro Building
Title: Soft Error Rate : Architecture, Modeling and Circuit Challenges
Abstract:
Soft errors in scaled technologies beyond 90nm are posing a
major challenge for design of memories and logic in future high
performance microprocessors. Historically, we had to consider
power-performance-area tradeoff. There is a need to consider soft error
rate (SER) as another design parameter. We describe both cosmic ray and
alpha-particle induced soft errors, an experiment to characterize
bit-level SER and a method to compute SER of large circuit blocks. We
also present scaling trends and SER-tolerant architecture/circuit
techniques.
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Li-Shiuan Peh
Princeton University
Date: Friday April 23, 2004, 2:30pm
Place: Interschool Lab (7th Floor), Schapiro Building
Title: Addressing the Power and Thermal Impact of Networks in Multi-Core
Processor Chips
Abstract:
As processors move towards multi-core designs, on-chip interconnection
networks are becoming the critical communication backbone that
facilitates collaborative processing among the cores. In this talk, I'll
address the power and thermal impact of these chip-scale networks,
starting with several case studies highlighting the power and thermal
contribution of these networks, along with details of our architectural
network power and thermal models.
Next, two distributed, collaborative approaches towards realizing power
and thermal-aware networks will be discussed -- First, a design
methodology we propose for power-aware networks with links turned
dynamically on/off in response to actual utilization; Second, a
run-time thermal management protocol towards regulating network
temperature. Finally, I'll touch on how we see the distributed,
collaborative approaches towards power and thermal-aware networks
forming the foundation for entire power and thermal-aware
multi-core processor chips.
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Stewart S. Taylor
Intel Corporation
Date: Friday April 16, 2004, 2:30pm
Place: Interschool Lab (7th Floor), Schapiro Building
Title: FET Noise Modeling and LNA Design
Abstract:
The RF performance of scaled CMOS continues to improve. For some of us, the sources
of noise in a FET appear complicated and mysterious. Worse, our intuitiion and
insight into what we can do to improve noise figure (NF) in a low noise amplifier
(LNA) may be lacking. This presentation will review basic noise models in MOSFETs,
and interpret them as they apply to a narrow-band LNA. Additionaly, an approach to
optimizing an LNA for low noise figure will be presented. The important difference
between optimizing a transistor for NFmin and optimizing an LNA for minimum noise
figure will be stressed.
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Ruchir Puri
IBM TJ Watson
Date: Friday April 9, 2004, 2:30pm
Place: Room 414 (4th Floor), Schapiro Building
Title: Design and CAD Challenges in sub-90nm CMOS Technologies
Abstract:
Fundamental limits have lead to the pessimistic predictions of the
imminent end of technological progress in semiconductor industry.
However, the push to scale conventional MOSFET has continued to show
remarkable progress. Continued scaling and demand for performance
are pushing for lower supply voltage and Vt, shorter channel length,
and thinner gate oxide. In addition, new device structures such as
double-gate FinFETs and 3D circuits are being aggressively pursued
for 65nm technology and beyond. Such aggressive scaling and new device
structures give rise to several unique design issues which must be
dealt with before any of these technologies will gain mainstream
acceptance. We will discuss unique design aspects and issues resulting
from this scaling such as power dissipation, gate-to-body tunneling,
self-heating, reliability issues, and process variations. With an eye
towards the future, design and CAD issues related to sub-65nm device
structures such as double gate FinFET will be discussed.
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Jaesik Lee
Bell Labs - Lucent Technologies
Date: Friday March 26, 2004, 2:30pm
Place: Room 414 (4th Floor), Schapiro Building
Title: High Speed A/D Converters for Broadband Communication Systems
Abstract:
High performance analog-to-digital converter (ADC) is a key circuit in
today's signal processing systems, for commercials and defense systems.
The ADC keeps extending its applications and performance with the
development of new material, technologies, architectures, and circuit
techniques. In particular, emerging telecom systems demand state-of-art
high speed and high resolution ADCs. This talk deals with design aspects
of today's most popular integrated ADC applications, technologies,
architectures, and circuits. First I present an overview of the various
ADC applications, technologies, architectures, and their performance
limitations. I then discuss the design considerations for 10GSPS ADCs for
optical receiver applications. Finally, I discuss the performance
requirements of the ADCs in RF applications and show two ADC examples for
IF sampling and even direct RF sampling receivers.
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Prof. Paul Hasler
Georgia Institute of Technology
Date: Friday March 19, 2004, 2:30pm
Place: Interschool Lab (7th Floor), Schapiro Building
Title: Programmable Analog Circuits for Cooperative Analog-Digital Signal
Processing
Abstract:
New advances in analog VLSI circuits have made it possible to perform
operations that more closely reflect those done in DSP applications, or that
are desired in future DSP applications. The recent explosion of advances in
floating-gate technology fabricated in standard CMOS processes have resulted
in analog circuits and systems that can be programmable, reconfigurable, and
adaptive at a density comparable to digital memories. Therefore, one might
wonder if we have both digital and analog signal processing available, how
does one choose a particular solution for a given application. This talk
will discuss our current research looks at these Cooperative Analog Digital
Signal Processing (CADSP) systems that benefit from the advantages of both
types of systems to make something better than the sum of its parts. We
will also describe basic floating-gate circuits, programming methods of
floating-gate circuits and systems, and how they enable a wide range of
circuit and signal processing operations. We will describe approaches
towards auditory and image signal processing applications, including
programmable filters, noise suppression, analog signal processing front-end
system for speech recognition, separable image transforms, and adaptive
filters. These approaches offer the possibility of changing the way we see
analog circuit design, as well as the future of analog and digital signal
processing.
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Prof. Mitiko Miura-Mattausch
Hiroshima University
Date: Friday March 12, 2004, 2:30pm
Place: Room 414 (4th Floor), Schapiro Building
Title: MOSFET Modeling for the RF Circuits Era
Abstract:
This presentation addresses observed phenomena obstructing
circuit performance in the RF operation regime. The origin of the
phenomena as well as their modeling will be discussed.
To assist in the development of RF circuits, the most important
issue is to guarantee sufficient simulation accuracy and
applicability for any advanced technology. Under high-frequency
operation, higher-order phenomena such as distortion as well as
noise become serious for reliable circuit performance prediction.
Here all such device phenomena are demonstrated to be determined
by carrier dynamics, which are in principle observed in the I-V
characteristics.
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Azeez Bhavnagarwala
IBM
Date: Friday March 5, 2004, 2:30pm
Place: Interschool Lab, 7th Floor, Schapiro Building
Title: Scaling Limits and Energy Efficient Solutions for CMOS SRAM Caches
Abstract:
Lowering the energy consumed by an SRAM cache in active or standby mode
is becoming increasingly difficult with scaling of transistor dimensions,
operating voltages and cache densities due to limitations imposed by VT fluctuations
in small-geometry cell transistors, by leakage due to thermal excitation
and quantum tunelling, by soft-error and by wiring.
This seminar will review fundamental limits on CMOS SRAM
operating voltages imposed by binary signal quantization
requirements, fluctuation limits on CMOS SRAM density imposed by
random VT fluctuations of CMOS SRAM cell transistors and
circuit techniques to reduce array leakage without impacting
performance, density or noise margins.
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David A. Rich
Lafayette College
Friday January, 2004 2.30pm
Room: 414 Schapiro Building (CEPSR)
A Virtual Loudspeaker MOdel to Enable Real-Time Listening Tests in Examining the Audibility of High-Order Crossover Networks
Abstract:
Two or more drivers are needed to cover the range of frequencies produced
by musical instruments. A loudspeaker's crossover network is an
electronic circuit that determines how the spectral region of the sound is
parsed among the speakers.
Linkwitz-Riley (L-R) crossover networks have proven successful in many
loudspeaker designs. They yield an all-pass response, and the driver
outputs remain in phase at the crossover point. Increasing the order of
the crossover reduces interference between drivers. L-R crossovers are
often designed to be fourth order; higher-order networks are rarely used
since the filter realization is often complex and expensive. Recently,
Thiele demonstrated that crossover networks with notched responses attain
sharper transition bands while retaining the favorable L-R
characteristics. Thiele networks with finite transmission zeros are
derived from L-R networks without finite zeros.
The effects of non-coincident drivers (i.e., drivers spaced across the
baffle of the loudspeaker) cause deep spectral notches to occur
intermittently in the crossover region depending on the path delay between
the loudspeakers individual drivers and the summed response at the
listener's ear. One objective of this talk is to demonstrate that
higher-order networks with zeros in the stop-band more consistently retain
a desired all-pass response of loudspeakers by limiting the frequencies at
which the drivers overlap and interfere with each other. A disadvantage
of higher-order networks is that the large phase variations across the
frequency spectrum are introduced in the loudspeaker's transfer response.
To evaluate the sonic impact of the deep spectral nulls and phase
varaiations to the overall listening experience, we employ a real-time
listening test that does not involve the design of real loudspeakers or
modification of a loudspeaker's sound in a listening environment. A
speaker-system simulation program, formulated in Matlab, processes
wavfiles of music clips with a virtual loudspeaker model that covers real
crossover networks, offset delays, compensation networks, and raw driver
frequency response characteristics. Double-blind testing methodology is
applied to determine the audibility of the virtual loudspeaker model under
test. The use of a double-blind technique distinguishes our tests from
those used by most audiophiles, as sighted listening tests often result in
wrong conclusions. We opine that the double-blind listening tests can
guide the designer to the simplest crossover network design that is
sufficiently robust to satisfy the majority of listeners.
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Alyssa Apsel
Assistant Professor, Cornell University
Thursday January 15, 2004 2.30pm
Room: Interschool Lab, CEPSR
Optics Within CMOS Microsystems: Design, Analysis and construction of Short Distance Optical Interconnects
Abstract:
Internal data rates of processors fabricated in deep submicron CMOS
technology have exceeded gigahertz rates. While processing proceeds at
gigahertz internally, off chip wires have held inter-chip clock rates
in the hundreds of megahertz. The rate of inter-chip communication is
now the bottleneck in high performance systems.
Optical inter and intra-chip communication has the potential to solve
many interconnect problems. Inter-chip optoelectronic communication
is complicated by the difficulty of routing bidirectional optical signals
in parallel around substrates. Furthermore, at the intra-chip level the
cost of hybridization and routing optical signals into detectors
presents an even larger problem.
In this talk, I focus on applications for and approaches to solving both
inter-chip and intra-chip communication problems by effective optoelectronic
interconnect design. This approach is multifaceted. First, I will discuss
design of chip-to-chip interconnects using ultra-thin silicon-on-sapphire
CMOS technology. I present designs and results of circuits that exploit
both the optical and insulating properties of the sapphire substrate to
implement short and middle distance optoelectronic links. Interconnects
constructed in this way avoid conventional CMOS routing and speed limitations.
Second, I will consider various interconnect architectures for power efficient
short and middle distance bit transfer in the context of an optical link.
Finally, I will discuss the potential for even shorter intra-chip interconnects
within optoelectronic microsystems, unique benefits of optics that can be
exploited in these systems, and future work in this area. By examining
the problem of optoelectronic interconnect design from three angles;
I hope to promote a deeper understanding of the overlapping issues concerned
in design of highly connective systems for the future of CMOS electronics.
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