Research Seminars
  Fall 2008

I will present our recent work that showcases how silicon RF chips can be used not only for wireless RF applications, but also for biosensing aimed at early disease detection. The main function of our RF chip is to manipulate and monitor RF dynamics of protons in water via nuclear magnetic resonance (NMR). Target biological objects such as cancer marker proteins and viruses alter the proton dynamics, which is the basis for our biosensing. The RF chip has a receiver noise figure of only 0.6 dB. This high sensitivity made possible our construction of an entire NMR system around the RF chip in a 2kg portable platform, which is 60 times lighter, yet 60 times more sensitive than a state-of-the-art commercial benchtop NMR system. Sensing one avidin protein molecule in 40 trillion water molecules, our system is a circuit designer's approach to pursue early disease detection and improved human healthcare.

Donhee Ham is John L. Loeb Associate Professor of the Natural Sciences and Associate Professor of Electrical Engineering at Harvard University. He earned his degrees in physics and electrical engineering, studying at Seoul
National University and California Institute of Technology. His current research focus is on (1) RF/microwave, analog, and mixed signal ICs, (2) GHz/THz 1-dimensional electronic and plasmonic transport, (3) soliton electronics, and (4) applications of CMOS ICs in biotechnology.

Research web: http://www.seas.harvard.edu/~donhee
Donhee Ham: http://www.seas.harvard.edu/~donhee/donheeham.htm

I present a flavor of Silicon-On-Insulator (SOI) technologies called Silicon-On-Sapphire (SOS), describing the fabrication process, the advantages and the basic devices available for circuit and micro-system design.

The physical differences in the fabrication of the SOS devices and the insulating substrate make this process quite different from a standard bulk process. The insulating substrate, the floating body and the different thermal properties of the sapphire give rise to characteristics that have to be fully mastered to allow for the design of high-performance circuits.

By taking advantage of the features and novelty of this integrated circuits process, I will introduce our success stories and a repertoire of state-of-the-art circuits and systems, such as: analog to digital conversion systems, ADC architectures, photodetectors, optoelectronic system, image sensors, biosensor interfaces, patch-clamp amplifiers, isolation amplifiers, temperature sensors, band-gap references, and three-dimensional circuits.

Abstract

There has been a resurgence of interest in asynchronous (i.e. clockless) digital design in recent years, as designers confront formidable challenges of high-speed clock distribution, chip complexity power, design time, mixed-timing domains and reusability. Asynchronous circuits are inherently concurrent, distributed and object-oriented, and thus promise much greater adaptability in assembling future-generation digital systems.

This talk is in two parts.  In the first part, I will give an overview of asynchronous design, including motivation, technical background and highlights of recent successes in industry (Philips, Fulcrum Microsystems, Intel, IBM) and academia. I will also briefly survey some active research areas: CAD tools for asynchronous circuits and systems, mixed-timing interfaces, high-speed asynchronous pipelines, and performance analysis.

In the second part, I will present one of our new design styles for high-speed asynchronous pipelines, called MOUSETRAP.  These pipelines use simple transparent latches in the datapath, and small latch controllers consisting of only a single gate per pipeline stage.  This simple stage structure is combined with an efficient transition-signaling protocol between stages.  Extensions to handling non-linear structures (fork, join) are introduced to handle more complex system architectures. The new pipelines gracefully and robustly adapt to variable-speed environments, such as due to dynamic voltage scaling. Post-layout simulations indicate throughputs of 2.1-2.4 GigaHertz in a conservative 0.18 micron CMOS TSMC process.  This performance is competitive even with that of "wave pipelines",  without the accompanying problems of complex timing and much design effort.

Speaker Biography

STEVEN M. NOWICK is a Professor of Computer Science and Electrical Engineering at Columbia University, and Chair of the Computer Engineering program. He received a Ph.D. in Computer Science from Stanford University in 1993, and a B.A. from Yale University.   Dr. Nowick's main research focus is on design methodologies and CAD tools for the analysis, synthesis and optimization of asynchronous and mixed-timing digital systems.

Dr. Nowick received an NSF Faculty Early Career (CAREER) Award (1995),
an Alfred P. Sloan Research Fellowship (1995) and an NSF Research Initiation Award (RIA) (1993).  He received Best Paper Awards at the 1991 International Conference on Computer Design and at the 2000 IEEE Async Symposium.   He was the recipient of 2 medium-scale NSF ITR awards in 2000 for asynchronous research, and in 2005 was brought onto the DARPA "CLASS" project, headed by Boeing, to create a new commercially-viable CAD tool flow for designing asynchronous systems.
Dr. Nowick was also a co-founder of the IEEE Async Symposia series, and was Program Committee Co-Chair of Async-94 and Async-99 and General Co-Chair of Async-05, and was Program Chair of the ACM IWLS-02 Workshop.  He is an associate editor of IEEE Transactions on Computer-Aided Design, and formerly associate editor of IEEE Transactions on VLSI Systems. He is an IEEE fellow.

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Abstract

We present a low power analog adaptive equalization technique suitable for combating inter-symbol-interference at very high data rates. The proposed technique, which we term the lumped parameter equalizer, addresses several of the problems associated with conventional microwave equalizers based on the tapped delay line structure. The theory is given, and simulation results comparing it with the performance of ideal tapped delay line filters are shown. Circuit implementations are discussed, along with the effect of nonidealities on equalizer performance.

Shanthi Pavan received the B.Tech degree in electronics and communication engineering from the Indian Institute of Technology—Madras, Chennai, India, in 1995 and the M.S and Sc.D degrees from Columbia University, New York, in 1997 and 1999, respectively. He has worked at Texas Instruments and Bigbear Networks, where he researched on high-speed analog filters and data converters. Since July 2002, he has been with the Electrical Engineering Department, Indian Institute of Technology—Madras, where he is an Assistant Professor. His research interests are in the areas of high-speed analog circuit design and signal processing.

Abstract


Manufacturing defects or errors due to transient phenomenon can impact the correct operation of asynchronous circuits. I will present an overview of the impact of these errors on the operation of asynchronous circuits, and in particular on quasi delay-insensitive asynchronous circuits. I will present a range of techniques for managing different types of failure mechanisms in asynchronous circuits.