Research
Seminars
Fall
2010
Previous
Seminars
Dr. Sherief Reda
Brown University
Date: December 3rd, 02:00pm, CEPSR 414
Topic: Addressing the
Thermal and Power Challenges of Tera-Scale Computing
Abstract
Power and temperature are major physical
challenges that need to be addressed in current and future computing
systems. In this talk three synergistic techniques will be presented to
address these challenges, including:
(1) Thermal characterization techniques to identify the locations of
temperature hot spots in real processors, and to use these locations to
drive an optimal thermal sensor allocation technique.
(2) Dynamic thermal management techniques for multi-core processors
where the performance of a real
processor is optimally adapted depending on thermal slack measured by
the thermal sensors during runtime.
(3) Post-silicon power modeling techniques where accurate spatial power
estimates for various circuit blocks are computed using the measured
thermal infrared emissions from the backside of the die.
In addition, the experimental techniques required for infrared imaging
and power acquisition of real systems will be overviewed. Our current
research on devising improved energy-proportional computing systems for
data centers will be also overviewed.
Biography
Sherief Reda is an assistant professor
of Electrical Sciences and Computer Engineering at the School of
Engineering, Brown University, where he heads the SCALE laboratory
(http://scale.engin.brown.edu). Professor Reda received his Ph.D.
degree in computer engineering from UCSD in 2006. His research
interests include physical design and management of computing systems,
variability modeling and yield improvement techniques for planar and
3-D integrated circuits, and reconfigurable computing. He has received
four best paper nominations and two best paper awards at DATE’02 and
ISLPED’10 and a NSF CAREER award.
Dr. Yun Chiu
University of Texas at Dallas
Date: November 12th, 02:00pm, CEPSR 414
Topic: Robustness and
Resiliency of Data Conversion
Abstract
As the performance and cost-per-function
continue to excel for microelectronic devices, the underlying economic
driving force is rapidly adapting the fabrication technology to meet
the critical needs of the industry. Our past research has shown that
with the leverage of system-level and digital techniques, energy
efficiency can be continually accelerated for data conversion circuits
in scaled technology nodes. While the approach is making significant
progresses in marching the benchmark of CMOS ADC figure-of-merit (FoM),
a paradigm-shifting challenge has emerged in the nano-scale regime and
beyond: analog robustness and resiliency, in the headwind of
exponentially growing process/device variability and degrading
operation environment due to mixed-signal integration. In this talk, I
will identify a few architectural and circuit techniques to cope with
the new challenges in the data conversion area. The focus will be
placed on redundant analog architectures and judicious application of
digital techniques for error correction. Some prototype results will be
showcased during the talk
Biography
Yun Chiu received his Ph.D. degree in
electrical engineering and computer sciences from the University of
California at Berkeley. He worked as a Senior Staff Member at a
start-up company in Fremont, California developing CMOS digital imaging
products from 1997 to 1999. Dr. Chiu was an assistant professor in the
ECE Department of the University of Illinois at Urbana-Champaign from
2005 to 2010. He is now with the Texas Analog Center of Excellence
(TxACE) of the University of Texas at Dallas, where he is an associate
professor of the EE Department and holds the TxACE Endowed
Professorship of Electrical Engineering. Dr. Chiu received the Jack
Kilby Award from the 2005 International Solid-State Circuits
Conference, the 2009 ISSCC/DAC Student Design Contest Award, and the
Agilent Foundation Award in 2009. He was an Associate Editor of the
IEEE Transactions on Circuits and Systems II: Express Briefs, and has
served on the technical program committees of the IEEE Custom
Integrated Circuits Conference, Asian Solid-State Circuits Conference,
etc. Dr. Chiu is an IEEE senior member and the author of the book
Analysis and Design of Pipelined Analog-to-Digital Converters
Dr. David Wentzloff
University of Michigan at Ann Arbor
Date: October 15th, 03:00pm, Interschool
Lab
Topic: All-Digital RF
Circuits Synthesized from Digital Standard Cell Libraries
Abstract
RF front-end circuits designed today for
operation in the 1 to 10GHz range are almost exclusively fabricated in
CMOS processes. This includes low-noise and power amplifiers, mixers,
oscillators, A/D converters... all the components that allow radios to
communicate wirelessly. Traditional design of these RF components
relies on precise RF models, high-quality passives, and time-consuming
custom layout for matching and controlled parasitics. The basic
building blocks used to realize these RF components are, not
surprisingly: transistors, resistors, inductors, and capacitors.
CMOS logic has become so fast, it is now realistic to design logic
using full-swing CMOS standard cell libraries that switch a >10GHz
speeds. CMOS logic has become so small, we can now fit 1000's of gates
in the area occupied by 1 inductor. As RF circuit designers, we can
think about how to accomplish the same functionality of an RF
front-end, but do so with a new set of basic building blocks: NAND,
tri-state buffers, flip-flops, etc. This could allow us to describe RF
circuits as a netlist of only logic gates, which in-turn enables fully
automated layout with digital CAD tools. Benefits include reduced chip
area, which will continue to shrink with process scaling. With smaller
area also comes lower power. This talk will present several
implementations of all-digital RF circuits synthesized from digital
standard cell libraries. A UWB transmitter, time-to-digital converter,
and PLL in 65nm CMOS will be presented, as well as an FM radio in an
FPGA. The core tuning structures and the calibration technique will be
described, which allows the circuits to be precisely regulated over
process, voltage, and temperature variations.
Biography
David D. Wentzloff received the B.S.E.
degree in Electrical Engineering from the University of Michigan, Ann
Arbor, in 1999, and the S.M. and Ph.D. degrees from the Massachusetts
Institute of Technology, Cambridge, in 2002 and 2007, respectively. In
the summer of 2004, he worked in the Portland Technology Development
group at Intel in Hillsboro, OR. Since August, 2007 he has been with
the University of Michigan, Ann Arbor, where he is currently an
Assistant Professor of Electrical Engineering and Computer Science. He
is the recipient of the 2002 MIT Masterworks Award, 2004 Analog Devices
Distinguished Scholar Award, 2009 DARPA Young Faculty Award, and the
2009-2010 Eta Kappa Nu Professor of the Year Award. He has served on
the technical program committee for ICUWB 2008-2010. He is a member of
IEEE, IEEE Circuits and Systems Society, IEEE Microwave Theory and
Techniques Society, IEEE Solid-State Circuits Society, and Tau Beta Pi.
Dr. Un-Ku Moon
Oregon State University
Date: September 17th, 3:00pm, Interschool
Lab CESPR/Schapiro
Topic: Emerging ADCs
Directions
This seminar is part of
the distinguished lecture series sponsored by the New York chapter of
the IEEE EDS/SSCS, please visit http://edssscs.googlepages.com/
Abstract
Most analog IC designers and students
are drawn to ADCs. While some ADC realizations have had a lasting
impact, examples including pipelined ADCs with digital redundancy,
flash ADCs with folding and interpolation, and multi-bit delta-sigma
modulators with dynamic element matching, there are many more recent
and emerging ADC design techniques that are receiving much attention
and also gaining momentum in some areas. Many of these ideas are
showered with doubts and honest criticism. However, we may also
be entering a new phase where a few of these developments would help
resolve the tough submicron scaling challenge that analog designers
face today. This tutorial will summarize and ponder the impact of
a few selective as well as random slices of these emerging ADC designs.
Biography
Prof. Un-Ku Moon has been with the
Oregon State University since 1998. Prior to that, he was with
Bell Labs from 1988-1989 and 1994-1998. He received a bachelor's degree
from the University of Washington, a master's degree from Cornell
University, and a Ph.D. from the University of Illinois,
Urbana-Champaign. His current research activities are found at
http://eecs.oregonstate.edu/~moon/research.
Refreshments will be
served.
Dr. Ram Krishnamurthy
Intel Labs, Intel
Coproration
Date: September 2nd, 11:00am, 627
Seeley W. Mudd
Topic: High-performance
energy-efficient reconfigurable accelerators/co-processors for
tera-scale multi-core microprocessors
Abstract
This seminar will present
multi-core microprocessors integrated with on-die
energy-efficient reconfigurable accelerator and co-processor
engines to achieve well beyond tera-scale performance in sub-45nm
technologies. Recent trends and advances in multi-core microprocessors
will be presented, followed by key enablers for reconfigurability of
specialized hardware engines to support multiple protocols while
substantially improving time-to-market and amortizing die area cost
across a wide range of compute workloads and functions. Specific design
examples and case studies supported by silicon measurements will be
presented to demonstrate reconfigurable engines for wireless baseband,
signal processing and graphics/media applications. Power efficient
optimization of reconfigurable processors to support fine-grain power
management, dynamic on-the-fly configurability and standby-mode leakage
reduction and low-voltage operability will also be described.
Biography
Dr. Ram K. Krishnamurthy is a
Senior Principal Engineer with the Circuits and Systems
Research Labs, Intel Corporation, Hillsboro, OR, where he
heads the high-performance and low-voltage research group. He
received the B.E. degree in Electrical Engineering from Regional
Engineering College, Trichy, India, in 1993, and the Ph.D. degree in
Electrical and Computer Engineering from Carnegie Mellon University,
Pittsburgh, PA, in 1998. He has been with Intel Corporation since 1998.
Past
seminars
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