The ISSCC offers local SSCS chapters the opportunity to replay  ISSCC tutorials, short courses and sessions based on the DVD  recordings. We will play the "Embedded Power-Management Circuits"  Tutorial by Prof. P. Mok from the ISSCC'07 in this event.

Tutorial Abstract :
Due to the drastic increase of system integration and power consumption of an IC with technology scaling, power management becomes a critical issue in determining the overall performance of the IC. This tutorial starts with a brief overview of power management circuits for embedded applications. There follows a  detailed explanation of the operation and design issues associated  with various on-chip power converter circuits including linear  regulator, switched-inductor regulator, and switched-capacitor  regulator. The focus is on the analog circuit techniques, and the control mechanism for implementing these power converters.

Abstract:
Variability is poised to severely degrade performance and power scalability of circuits and systems in nanoscale CMOS technologies. Process, voltage, and temperature variations are well-known effects that occur across wide temporal and spatial scales.  With aggressive technology scaling, traditional worst-case design techniques incur large overheads.  Higher-level solutions, combined with innovations at the circuit level, offer a holistic approach that should combat and mitigate the detrimental effects of variablity.  This talk presents a broad perspective of how we leverage collaborations between circuits and architecture to address varibility in different contexts.
    Random and systematic variation can can degrade power and performance of digital systems.  This talk introduces ReVIVaL, which incorporates two techniques to combat variability---voltage interpolation and variable latency. When applied to a 6-stage floating-point unit (FPU), experimental results from a 130nm test chip demonstrate how these techniques can compensate for random and correlated device-level variations without compromising performance. We also explore the potential benefits of ReVIVaL extended to a CMP system. Besides process variation, voltage variation can also degrade performance scalability and require power overheads.  Hence, we investigate the potential energy savings offered by temporally fine-grained, per-core DVFS using integrated on-chip switching regulators.  Our analysis suggests energy savings are possible through fast, per-core DVFS despite the overheads associated with lower-effiency on-chip regulators. Finally, I will summarize other research efforts we have on-going at Harvard.

Bio:
Gu-Yeon Wei joined Harvard University in January 2002 and is currently an Associate Professor of Electrical Engineering. Prior to joining Harvard,  he spent 18 months at Accelerant Networks in Beaverton, Oregon. Professor Wei received his BS, MS, and PhD degrees in Electrical Engineering all from Stanford University in 1994, 1997, and 2001.  His current research interests are in the areas of mixed-signal VLSI
circuits and systems design for high-speed/low-power wireline data communication, energy-efficient computing devices for sensor networks, and collaborative software + architecture + circuit techniques to
overcome variability in nanoscale IC technologies.

Host:  Ken Shepard, shepard AT ee DOT columbia DOT edu, 212-854-2529

Future "end-of-scaling" CMOS technologies are characterized by three major themes: 1)abundant transistors, such that they can be placed almost  anywhere with little cost; 2)power constrained, exacerbated by the cease in supply scaling; 3) process variant, where what you simulate is not what you get. In addition, passive interconnect (both on-die and off-die) exhibit degraded performance relative to transistor scaling, making interconnect circuits one of the key circuit blocks that exhibit firsthand these three scaling constraints. Multi-core computing can improve parallel performance only at the expense of larger reliance on interconnect circuits.  Therefore, the design of interconnect circuits that can address these three issues is paramount. In this talk, I will describe a number of ways the VLSI group at Oregon State is tackling these three key problems.  First, leveraging past work, I will describe a few ways we have recently addressed these issues, resulting in a few initial (but un-measured) 65nm CMOS prototypes:  10GSs, 4-bit, 35mW ADC using resonant clocking; 10 parallel, 10Gbps Transmitters dissipating 40mW.  Finally, I will describe future areas of research that we believe are key circuit challenges for future interconnect-limited, parallel architectures - SRAMs, crossbars, on-die serial links, off-die serial links, ADCs, and speed-of-light circuits.

Patrick Chiang received the B.S. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 1998, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 2001 and 2007.  He is currently an assistant professor of electrical and computer engineering at Oregon State University. In 1998, he was with Datapath Systems (now LSI Logic), working on analog front-ends for DSL chipsets. In 2002 he was a research intern at Velio Communications(now Rambus) working on 10GHz clock synthesis architectures. In 2004 he was a consultant at startup Telegent Systems, evaluating low phase noise VCOs for CMOS mobile TV tuners. In 2006 he was a visiting NSF postdoctoral researcher at Tsinghua University, China, investigating low power, low voltage RF transceivers. In Summer 2007, he was a visiting professor at the Institute of Computing Technology, Chinese Academy of Sciences, where he collaborated on the design of multi-gigahertz ADCs and high speed serial links.

His interests are in the design and implementation of new architectures for mixed signal circuits in deep submicron CMOS, focusing specifically on low power consumption and process compensation techniques.

The problem of interference continues to become progressively severe in modern wireless systems, owing to greater utilization of spectrum. Simultaneously, the data rate in many systems continue to increase. Radio front-ends for such systems thus have to satisfy ever more stringent dynamic range requirements. This can pose an especially severe challenge in short-channel CMOS implementations, due to the relatively low supply voltages of these technologies.
Radio front-end architectures that can alleviate the above dynamic range challenge are presented in this talk. We begin by examining a low-power recursive radio front-end topology, that utilizes transconductance at multiple frequencies. The next part of the talk addresses our recent work in the area of radio front-ends that utilize feedforward auxiliary paths to cancel interferers at critical points with the receiver chain. The technique can be used for canceling multiple narrowband interferers as well as for achieving broadband attenuation, without the use of external passive SAW or ceramic filters and with minimal impact on in-band sensitivity. Recent work on combining active cancellation with interference detection is presented. An architecture for broadband interference sensing, that utilizes a cascade of image reject stages is also discussed.
It is expected that many of these approaches will be useful in emerging broadband wireless systems as well as Cognitive Radio and Software Defined Radio systems.

Dr. Ranjit Gharpurey is with the Dept of Electrical and Computer Engineering at the University of Texas at Austin. He received his PhD from the University of California at Berkeley in 1995 and his B. Tech from the Indian Institute of Technology, Kharagpur in 1990. His areas of research interest include RF and high-frequency analog IC design.
Dr. Gharpurey is currently serving on the technical program committees of CICC, ISSCC and RFIC conferences, and is an associate editor of the IEEE Journal of Solid State Circuits.

We discuss the role of biologically inspired spike representations in various engineering
applications including sensor design, time-based signal processing, and power-efficient
neural recording circuitry for brainmachine interfaces. These spike-based systems are
shown to outperform conventional approaches in terms of various performance metrics such
as power consumption, size, SNR, signal bandwidth and dynamic range. We also consider the
implications this work has on our understanding of neurobiological systems.

Speaker Bio:
Dr. John G. Harris received his BS and MS degrees in Electrical Engineering from MIT in
1983 and 1986. He earned his PhD from Caltech in the interdisciplinary Computation and
Neural Systems program in 1991. After a two-year postdoc at the MIT AI lab, Dr Harris
joined the Electrical and Computer Engineering Department at the University of Florida
(UF). He is currently a full professor and leads the Hybrid Signal Processing Group in
researching biologically-inspired circuits, architectures and algorithms for sensing and
signal processing. Dr. Harris has published over 100 research papers and patents in this
area. He co-directs the Computational NeuroEngineering Lab and has a joint appointment in
the Biomedical Engineering Department at UF.

Sponsored jointly by the Bionet Group (EE), CISL (EE) and LIINC Lab (BME)