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Seminars Spring 2003

Jesus A. del Alamo

Massachusetts Institute of Technology
Thursday May 29, 2003 2.30pm
Room: Interschool Lab, CEPSR

If You Can't Come to the Lab, the Lab Will Come to You! An Online Laboratory for Microelectronics Device Characterization


As a consequence of a variety of constraints, many subjects in science and engineering education do not include a laboratory experience. Yet, hands-on laboratory exercises can substantially enhance education effectiveness. At MIT, we are harnessing Internet technology to enable students to remotely access real laboratories and carry out experiments from anywhere at any time. This talk will describe and demonstrate the MIT Microelectronics WebLab, an online microelectronics device characterization laboratory. It will also discuss educational experiments carried out using WebLab from MIT, Singapore, and Sweden.

Chandu Visweswariah

IBM Thomas J. Watson Research Center
Fri May 9, 2003 2.30pm
Room: Interschool Lab, CEPSR

Death, Taxes and Failing Chips


In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important aspect of high-performance digital integrated circuit design, and indispensable for first-time-right hardware and cutting-edge performance. The presentation will discuss the methodology, analysis, synthesis and modeling aspects of this problem. These aspects of the problem will be compared and contrasted in the ASIC and custom (microprocessor) domains. Particular attention will be paid to statistical timing analysis; desirable attributes that would render such an analysis capability practical and accurate will be enumerated. The algorithms and activities being pursued in IBM to solve the statistical timing problem will be briefly discussed.

Sander Gierkink

Agere Systems
Fri May 2, 2003 2.30pm
Room: Interschool Lab, CEPSR

Recent developments in LC-tuned VCO design


With the emerging market for the wireless LAN standards 802.11a and g, the need exists to provide radio solutions that integrate these standards together with the popular "b"-standard into a single receiver. These so called "combo"-solutions pose stringent requirements on the radio's VCO in terms of phase noise and tuning range. Preferably a single VCO, in combination with selectable frequency division, provides the capability of covering all RF bands (respectively 2.412-2.484GHz and 5.18-5.805GHz for the b,g and a standard).

This talk will highlight some recent developments in the design of LC tuned VCOs. The first part of the talk will deal with the role that the varactor plays in the tuning linearity and noise upconversion of LC-tuned VCOs. The topics addressed will include: tuning dependency on bias current, linearization of the tuning curve when using varactors with an abrupt C(V) characteristic, bias noise upconversion by the varactor through AM-and CMM-to-PM conversion, and differential tuning as a way to reduce noise upconversion.

The second part of the talk will deal with quadrature oscillators. It will be shown how quadrature oscillators can be used with advantage in potential 802.11 architectures. After a brief overview of existing quadrature VCO topologies, an alternative concept of quadrature coupling of LC oscillators is introduced. It uses injection-locking through common mode inductive coupling to enforce quadrature. The technique provides quadrature over a wide tuning range without introducing any phase noise or power consumption increase.

Daniel Foty

Gilgamesh Associates (Fletcher, Vermont)
Fri April 25 2003 2.30pm
Room: 414 CEPSR

Building a New Framework for Deep Submicron Analog/RF CMOS Design and Beyond


At the present time, analog and RF CMOS design suffer from a variety of self-imposed constraints which severely limit both the efficiency of the design process and the capabilities of product ICs. These constraints are not real, but are instead self-inflicted due to the continued use of a design infrastructure which has been overstretched and which has outlived its usefulness. At its roots, the problem is one of an overly deconstructed and segmented approach to the MOS transistor in understanding, modeling, usage, and design implementation.

This presentation will outline a fundamental rebuilding and re-generalization of the entire approach to describing the MOS transistor and the methods by which the ubiquitous MOSFET is used in circuit design. Rather than being split up into separate pieces, this new approach involves the construction of an overarching structure through which process technology, modeling, design usage, and design optimization all become part of one coherent whole. It will be shown that not only can the MOS transistor be interpreted in a much simpler and more comprehensible fashion, but that this interpretation is universal across processes and technologies. Some examples, taken from real situations where ICs have been designed and sold in large quantities, will be described, clearly demonstrating how many of the self-imposed constraints of older methods can be broken, allowing for fuller use of the capabilities of modern deep-submicron CMOS technology. Finally it will be noted that by this generalization of the behavior of the MOS transistor, the methods thus developed can be generalized beyond CMOS to future nanotechnology devices.

Krishnamurthy Soumyanath

Intel Corporation
Fri April 18 2003 2.30pm
Room: Interschool Lab, 7th Floor CEPSR

Challenges and Opportunities for Mixed Signal Systems in Sub 100nm CMOS Technologies


The continued scaling of CMOS transistors provides significant challenges and opportunities for designers of mixed signal systems. We will review scaling trends and discuss its implications for incipient mixed signal systems. Using examples drawn from high- speed digital, low frequency as well as Radio frequency analog design applications, we will describe the impact of reducing voltages while simultaneously increasing leakage currents. We will also discuss, the space of realizable systems in the context of available device bandwidth and integration levels.

Professor Bradley Minch

Cornell University
Fri April 11 2003 2.30pm
Room: Interschool Lab, 7th Floor CEPSR

Low-Voltage Analog Circuit Design With Floating-Gate MOS Transistors


We design in the era of the ever shinking power supply. Many of the basic tried-and-true cells that are in our textbooks are or will soon be rendered unuseable due to this unrelenting downward march of Vdd. In the face of such challenges, some have suggested that floating-gate MOS (FGMOS) transistors are useful devices for designing low-voltage circuits, mainly because they offer us the possibility of lowering their threshold voltages by programming their floating-gate charges appropriately. However, since Shibata's introduction of the neuron MOS concept, we have realized that FGMOS transistors have more to offer than programmable threshold voltages. We can capacitively couple as many control gates as we would like into the floating gate of a FGMOS transistor, which opens up to us many new circuit topologies, many of which are very quite attractive for operation on a low power supply voltage. In this talk, I will discuss some of our recent efforts in charting this new design space.

Professor Yannis Tsividis

Columbia University
Fri March 28 2003 2.30pm
Room: Interschool Lab, 7th Floor CEPSR

Internally Varying Analog Circuits: A Means for Minimizing Power Dissipation


This talk examines the fundamental reasons for the large power dissipation of dynamical analog circuits with large dynamic range. It is shown that by allowing the internal attributes of circuits to vary in an appropriate manner, such fundamental limitations can be bypassed in certain cases. The talk reviews several techniques, developed by the analog group of CISL in the past several years, which make possible internally varying analog circuits with invariant external behavior. These techniques include companding, dynamic biasing, and dynamic impedance scaling. Experimental results from recently developed chips, which demonstrate over an order of magnitude improvement compared to the state of the art, are described.

Dr. Mehmet Soyuer

IBM T J Watson Research Center
Wednesday, Feb 21 2003 2.30pm
Room: Interschool Lab, 7th Floor CEPSR

High-Speed Link Technology Research at IBM


Advanced silicon technologies have opened the doors to implement very high-speed links for electrical, optical and wireless connections. In parallel to higher bandwidth requirements, there is also a pressing need for higher levels of integration in the wired and wireless communication fields to bring the cost and power dissipation down while still complying with stringent link requirements such as sensitivity, jitter and bit-error-rate.

In this talk, we will review the research activities undertaken by the Communication Circuits and Systems department at IBM T.J. Watson Research Center, Yorktown Heights, NY in the area of multi-Gb/s and microwave links using CMOS and SiGe technologies.

Dr. Philip N. Strenski

IBM T J Watson Research Center
Wednesday, Feb 07 2003 2.30pm
Room: Interschool Lab, 7th Floor CEPSR

Power-Performance Efficiency Studies


Power has emerged recently as a primary design variable in high-end microprocessors. Naive focus on performance leads the system design into inefficient power-performance operation. In order to design more effectively it is important to have power-performance measures to guide the design from technology through circuit design to micrarchitecture. The first part of the presentation highlights hardware intensity, a measure of the power-performance efficiency of a circuit design. Relations are derived using this measure which have practical consequences for power budgeting and for joint circuit-microarchitecture tradeoffs. The second part of the presentation focusses on adding power to the analysis of microarchitectural pipelining. The results illustrate the hazards of ignoring power, and the major impact it can have on optimal pipelining. The talk concludes with speculations on further research opportunities in this area.

G.W. den Besten

Philips Research Laboratories Eindhoven
Wednesday, Feb 05 2003 1.30pm
Room: CEPSR 414

The Future of Electrical Backplanes: High-Speed at Low-Cost


Backplanes contain a lot of interconnect to connect several system parts. The required data bandwidth of interfaces within/between systems continues to grow and therefore there is always a drive to increase backplane communication speed. Sometimes the question is posed whether this type of communication will be replaced by optical links soon.

This presentation shows that electrical is certainly not at its end of life. Proper signalling, transmission lines and characteristic design can boost the performance to 10Gb/s/channel (and probably beyond). Furthermore electrical has certainly a strong advance: low-cost. The presentation discusses several bus and signalling concepts, shows problems and limitations, but also solutions and opportunities for the future enabled by technology improvements. Optical links seem not really competitive yet for this kind of application. This brings up the conclusion that (new) electrical links remain the preferred solution for the foreseeable future.

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