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Seminars Fall 2003

Sharad Kapur

Integrand Software, Inc.
Date: Friday December 5th, 2003, 2:30pm
Place: Room 414 (4th Floor), Schapiro Building (CEPSR)

Title: Large Scale Full-Wave Extraction for RF and High-Speed IC Design


Accurate modeling of interconnect parasitics, passive components and passive component ensembles is a critical step in high-speed design. Traditional full Maxwell equation field solvers originating from the microwave community are accurate but are very inefficient and hence impractical to use for IC design. The current class of quasi-static solution techniques developed in the CAD community are efficient but often cannot meet the high-accuracy requirements of RF design. We introduce a new extraction tool EMX (ElectroMagnetic eXtractor) for the analysis of RF, analog and high-speed digital circuits. EMX uses a new version of a generalized Fast Multipole Method. It is a fast, integral-equation based, full-wave field solver which takes advantage of the layout ``regularity'' in typical design. In addition, a new formulation for the implementation of the vector Maxwell's equations is developed that significantly reduces computing resources. EMX is one to two orders of magnitude faster than the current class of approaches for solving similar problems. A number of designs such as inductors, Baluns, VCOs and RF Blocks have been simulated and designed with EMX and we show the comparison to measurement.

Bryan Ackland

Date: Wednesday December 10th, 2003, 11:00am
Place: Room 414, 4th Floor, Schapiro Building (CEPSR)

Title: Communications Systems on a Chip in the Post-Bubble Era


In the late 90's, communications was the fastest growing segment of the semiconductor industry driven by the internet boom and a perceived need for increased transmission, switching and processing capacity. Silicon providers focused on increasing port speed along with a reduced time to market. When the bubble burst, service providers cut back severely on capital expenditure and now look for new ways to increase revenue while reducing operating cost. In this new environment, silicon 'system on a chip' technology offers the possibility of increased functionality and flexibility while reducing overall system cost. This will be achieved using a combination of higher levels of integration, embedded software, reconfigurable hardware and new packaging technologies. This talk describes a number of examples of how system on a chip technology can be used to improve functionality while reducing overall cost in wired, wireless and storage applications. These examples will be used to identify some major architectural and implementation trends. Finally, we will take a look at some of the key challenges facing communication chip designers moving forward.

David Garret

Bell Laboratories, Lucent Technologies
Date: Friday December 12th, 2003, 2:30pm
Place: Interschool Lab, 7th Floor, Schapiro Building (CEPSR)

Title: Silicon Chips for MIMO Receivers


One of the big advances in wireless communication in recent times involves the use of multiple transmit antennas to realize enormous gains in spectral efficiency. Multiple-input multiple-output (MIMO) wireless systems generalize the concept of the Bell Labs Layed Space-Time (BLAST) coding scheme for spatial multiplexing. This talk will highlight algorithms and architectures for MIMO receivers that have been used to implement practical MIMO receivers in silicon. The results are shown in the context of the high speed downlink packet access (HSDPA) extension of UMTS for 3rd generation mobile communication, with a silicon chip that can achieve up to 28.8 Mb/s over a 5 MHz channel using up to a 4x4 QPSK MIMO configuration (5.76 bits/s/Hz). Some of the significant challenges include dealing with the self-interference caused by the loss of orthogonality between the spreading codes from a frequency-selective channel and implementing exponentially complex maximum likelihood (ML) MIMO detection algorithms efficiently in hardware. The talk will describe the key features of the ASIC and present some preliminary over-the-air measurements that attest to the performance of MIMO for HSDPA. Furthermore, the talk will highlight future implementation techniques for achieving even higher spectral efficiency by using “spherical” decoding techniques for MIMO receivers. Spherical decoding allows near-ML performance with only a fraction of the complexity for MIMO configurations like 4x4 16QAM, or 8x8 QPSK, which are much too complex to compute directly with ML.

Kevin Kornegay

Cornell University
Date: Monday December 15th, 2003, 1:00pm
Place: Room 414, 4th Floor, Schapiro Building (CEPSR)

Title: Research Highlights of the Cornell Broadband Communications Research Laboratory


The mission of the Cornell Broadband Communications Research Laboratory (CBCRL) is to develop fundamental device, circuits and systems knowledge in broadband communications systems by understanding issues that impact the design of high performance, energy efficient wireline and wireless systems. This talk will highlight some of the ongoing research activities, particularly our low power 3G WCDMA receiver, 60 GHz radio, and 10 Gb/s low power integrated optical transceiver work. The design challenges associated with each of these activities are presented along with mixed-signal circuit solutions that are used or proposed to overcome them.

Dr. Hans Georg Brachtendorf

Fraunhofer Institute IIS-A, Erlangen, Germany
Date: Monday December 24th, 2003, 3:00pm
Place: Room 425 (4th Floor), Pupin Building

Title: Frequency Entrainment: Theory and Applications


The understanding of synchronization mechanisms is mandatory in the design of a lot of technical systmes such as PLLs, in the suppresion of phase noise, e.g. in injection locked lasers, in stimulating the heart by an external electrical impulse by a pacemaker and so on.
The underlying physical effect is referred to as injection locking or frequency entrainment. In recent time injection locking has been applied to the design of quadrature oscillators with low phase-noise and in novel concepts for receiver synchronisation. From a circuit designer's viewpoint the knowledge of the locking range is extremely important.
In our talk we first review different ways of understanding this phenomenon. Based on that we give a general theory of entrainment based on Floque'ts theory of linear periodic time-varying systems. Based on this theory one obtains a simple differential equation which predicts the locking range reliably. Optimization with regard to system parameters can therefore be done easily. The accuracy of the method could be proven by comparison with a pure numerical method. Based on this, new circuit designs are investigated.

David M. Binkley

The University of North Carolina at Charlotte
Date: Friday November 21th, 2003, 3:00pm
Place: Room 414 (4th Floor), Schapiro Building (CEPSR)

Title: Optimizing Analog CMOS Design from Weak through Strong Inversion


Analog CMOS design has been traditionally taught assuming MOS strong inversion operation with square-law device characteristics. However, the high transconductance efficiency, moderate bandwidth, and low drain-source saturation voltage available in moderate inversion make this region increasingly important for power efficient, low voltage designs. Additionally, there is little or no strong-inversion, square-law region for small channel length devices due to velocity saturation and other small-geometry, high-field effects. As a result, there is a need for analog CMOS design methods that freely permit design in weak, moderate, and strong inversion, inclusive of velocity saturation, dc mismatch, flicker noise, and other advanced effects. In the methods described in this seminar, the inversion coefficient is used as a numerical measure of MOS inversion level. Analog CMOS optimization is described where drain current, inversion coefficient, and channel length are used as the three degrees of design freedom with channel width easily determined as needed for layout. Optimized tradeoffs in gain, bandwidth, white and flicker noise, dc mismatch, drain-source saturation voltage, power efficiency, and other measures are presented. Additionally, measured 0.5- and 0.25-um transconductance efficiency, gm/ID, and normalized output conductance, VA = ID/gds, is presented from weak through strong inversion over a wide range of channel lengths. These measurements with comparisons to the EKV 2.6 and 3.0 MOS model provide a rich source of information for the modern analog designer. The design methods are illustrated on the design of three simple operational transconductance amplifiers designed for optimal bandwidth, optimal dc gain, dc mismatch, and flicker noise, and balanced bandwidth and dc performance. Finally, a CAD tool developed at UNC Charlotte is presented to guide the designer towards optimum analog CMOS design without the use of time-consuming, iterative circuit simulations.

Laurence W. Nagel

Omega Enterprises
Date: Friday November 7th, 2003, 2:30pm
Place: Interschool Lab (7th floor), Schapiro Building (CEPSR)

Is It Time for SPICE 4 ?


SPICE originally was released into the public domain in 1971 by the University of California, Berkeley. The program enjoyed almost instant acceptance, with universities all over the world employing the program in integrated circuit design courses as well as computer-aided design research. SPICE2 was released into the public domain in 1975, again by the University of California, Berkeley. SPICE2 also enjoyed wide acceptance, and after SPICE 2G.6, work on SPICE at Berkeley waned. Not until 1989, almost 15 years later, was SPICE3 released into the public domain by Berkeley. The latest public-domain SPICE3 simulator was released around 1993, about ten years ago. This talk will chronicle the crucial role SPICE had in launching a cottage industry of alphabet SPICE programs as well as hundreds of university research projects in various areas of circuit simulation. Paramount in this role was the fact that SPICE has always been in the public domain, available to all at a very nominal cost. SPICE-like programs, notably SPECTRE and ELDO, have been written since SPICE3 was released, but these follow-on programs are notably not in the public domain. The talk concludes by pondering the question of whether a more recent, public-domain circuit simulation program is necessary at this point.

Michael Perrott

Massachusetts Institute of Technology
Friday October 24th, 2003, 2.30pm
Interschool Lab (7th floor), Schapiro Building (CEPSR)

Design and Simulation of Phased Locked Loops


Phase locked loops (PLL) are used in a large variety of applications ranging from wireless and wireline data links to high performance microprocessors. It is quickly becoming clear that the performance of these circuits will dictate the achievable performance of many future systems since they will set the spectral mask and A/D performance achievable in future wireless systems, and the jitter levels achievable in future data link and microprocessor applications. Yet, despite their importance in current and future systems, today's design techniques are cumbersome and difficult for beginners, and current simulation techniques are slow and inaccurate when attempting to characterize both the dynamic and noise performance of PLL circuits. In this talk, we present a computer-aided approach to PLL system design that allows the user to quickly explore system level tradeoffs and to quickly assess, at the system level, the impact of nonidealities such as parasitic poles and parameter variations due to changes in process and temperature. We then present simulation techniques that allow fast and accurate characterization of PLL and DLL circuits at a behavioral level, with special focus being placed on fractional-N frequency synthesizers. Finally, calculated and simulated phase noise plots are compared to measured results of a custom fractional-N synthesizer to verify the accuracy of the presented techniques.

Marcel Pelgrom

Philips Research
Wednesday October 15th, 2003 2.30pm
Room: 414, CEPSR

CMOS Matching In The Digital Era


This talk will discuss some issues of (mis-)matching of CMOS transistors and the consequences for IC design. Stochastical fluctuations of especially the threshold voltage of CMOS transistors are considered one of the major bottlenecks in advanced CMOS design both for analog as well as for digital circuits. Next to a short introduction to the basic model, several examples of mis-matching circuits will be shown and design techniques and technological measures will be discussed. The trends in more advanced CMOS processes will be discussed briefly. The talk will start with a short introduction to Philips Electronics.

Omar Wing

Professor Emeritus, Columbia University
Friday October 10th, 2003 2.30pm
Room: Interschool Lab, CEPSR

A New Chaos Oscillator for Chaos Shift-Keying Communications


We present a new structure of chaotic oscillator and demonstrate its potential applications in chaotic digital communications with both coherent choas-shift-keying and non-coherent differential chaos-shift-keying. A new non-coherent communication method which detects binary digits according to the direction of rotation of the received signal is presented and we compare its performance with a conventional one based on correlation.

Siva Narendra

Microprocessor Research Lab, Intel Corporation
Friday September 12, 2003 2.30pm
Room: Interschool Lab, CEPSR

Silicon Integration Choices in Sub-45nm Power Limited Microprocessors


Traditional scaling of microprocessors relies on performance improvement of general purpose computations. This is achieved through augmented architecture and circuit design complexities, apart from device technology scaling. The performance improvement from architectural and circuit complexities increase demands higher level of integration and die size growth. Scaling of device technology results in increased sub-threshold and tunneling leakage currents. This combination of device scaling and integration trend results in ever increasing power consumption which cannot be sustained in the long run. Implementation of special purpose power efficient applications in future microprocessors enables us to add functionality without significant power penalty. In this talk, I will first highlight the above mentioned scaling trends and the resulting power challenges. Next, I will present the benefits of special purpose computation to achieve better power efficiency by highlighting two communication applications - TCP/IP network processing and Ultra Wide Band wireless protocol implementation.

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