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### Research Seminars Spring 2007

Mahbod Eyvazkhani, PhD.
Prinipal Scientist
Nokia Research Center, Palo Alto, CA.

Date: 2:00pm, Friday, June 15, 2007
Place: EE Conference Room, 1312 S.W. Mudd

Title:  Wireless Communication on 60 GHZ

With the availability of 7 GHz of unlicensed spectrum around 60 GHz, there is growing interest in using this resource for new consumer applications requiring very high data rate 2-10 Gb/s in wireless transmission. Systems communication design on 60 GHz has advantages and also some disadvantages. The challenges to meet appear not only on RF design but also on base band side. The different schemes on baseband architecture will be discussed considering their degree of complexity.

Mahbod Eyvazkhani has obtained his engineering diploma(M.Sc.), DEA and a PhD from Ecole Nationale superieure des Telecommunications (ENST-paris) in France. He was employed at Bell-Labs (Lucent Technologies), Globespan and two other start-up befor joining Nokia. He is currently working on mmWave wireless communication project (60GHz) as a principal scientist at Nokia Research Center in Palo Alto. His main interests include equalization, channel coding and modulation on communication systems with emphasis on analog and VLSI implementation.

Prof. Shanthi Pavan

Date: 2:00pm, Friday, May 25, 2007
Place: 414 CEPSR

Title:  Power Reduction in High Speed Flash Analog-to-Digital Converters using Distortion Correction

We present a flash ADC design technique that compensates for static nonlinearity of the up-front sample and hold circuit, so that high speed and high linearity can be obtained at the same time. This enables the use of a significantly larger input signal swing than would otherwise be possible, translating eventually into reduced power dissipation. The proposed technique functions in synergy with a new background comparator offset  correction scheme. We demonstrate the efficacy of our techniques with measurement results  from  a 160 Msps 6-bit flash converter designed in a 0.35-$\mu\rm{m}$  CMOS process. The ADC consumes 50~mW from a 3.3~V power supply and has an ENOB of  5.3 bits at Nyquist.

Shanthi Pavan  obtained the B.Tech degree in  Electronics and  Communication Engineering from the Indian Institute of Technology, Madras in 1995 and the M.S and Sc.D degrees from Columbia University, New York in 1997 and 1999 respectively. From 1997 to 2000, he was with Texas Instruments in Warren, New Jersey, where he worked on high speed analog filters and data converters. From 2000 to June 2002, he worked on microwave ICs for data communication at Bigbear Networks in Sunnyvale, California. Since July 2002, he has been with the Electrical Engineering Department of the Indian Institute of Technology-Madras, where he is an Assistant Professor. His research interests are in the areas of high speed analog circuit design and signal processing. Dr.~Pavan serves on the editorial board of the IEEE Transactions on Circuits and Systems: Part II - Express Briefs and is a recipient of the Young Engineer Award from the Indian National Academy of Engineering.

Edi Säckinger
Conexant Systems, Inc.

Date: 2:00pm, Friday, April 27, 2007
Place: 414 CEPSR

Title:  A 5-V AC-Powered CMOS Filter-Selectivity Booster for POTS/ADSL Splitter Size Reduction

An active POTS filter consisting of a small external L-C low-pass filter and a selectivity booster chip is presented. The filter achieves an ADSL attenuation of more than 70dB at 30kHz while maintaining a passband flatness of 0.2dB.

This active filter requires fewer transformers and is smaller than a passive filter with the same performance. The 0.5um CMOS booster chip contains a 5th-order continuous-time filter, a low output-impedance driver, and an active rectifier and consumes 50mW from a 5V AC supply.

Eduard Säckinger (S'84--M'91) was born in Basel, Switzerland. He received the Diploma and Ph.D. degrees in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, in 1983 and 1989, respectively. From 1989 to 2001, he was with the research division of Bell Laboratories in Holmdel, NJ where he worked on VLSI chips for artificial neural-networks and multiprocessor DSPs. In 2001, he became a Distinguished Member of Technical Staff with Agere Systems, Inc. where he worked on analog front-end chips for optical fiber communication systems. Since 2004, he is Principal Engineer for Mixed Signal Design at Conexant Systems, Inc. in Red Bank, NJ. He is the author of the textbook Broadband Circuits for Optical Fiber Communication (Wiley, 2005) and he serves as an Associate Editor for the IEEE Journal of Solid-State Circuits.

Prof. Thao Nguen
City College of New York

Date: 2:00pm, Monday, April 30, 2007
Place: Interschool Lab - 7th Floor CEPSR

Title:  Formal spectral theory for feedback systems with quantization (Sigma-Delta modulation)

A Sigma-Delta modulator is an analog-to-digital converter that includes a scalar quantizer in a feedback loop. This permits the achievement of high-resolution conversions with a coarse and imprecise quantization. The error analysis of this system however escapes from the existing signal and system theories. In the signal processing/communications area, only linear feedback systems are rigorously understood.

We build rigorous foundations to the error analysis of Sigma-Delta modulators by importing knowledge from dynamical systems into the classic linear system framework. We drop the standard signal processing approach, which looks at the quantizer error signal as the transformation of the input signal by some transfer function. Instead, we present this error signal as the output of an input-free and time-invariant dynamical system. This is possible in steady state when the input is a finite sum of sinusoids.

This new signal approach allows the use of "noble" mathematical tools such as functional analysis, for the rigorous analysis of quantization. This is a major contribution, as the discrete nature of quantization has prevented the use of continuous mathematics and has typically required the use of approximate and stochastic models (noise). Under the new framework, we derive rigorously quantization error spectra thanks to the powerful properties of unitary operators in Hilbert Spaces. The famous former work by Robert Gray and related authors performed in the special case of "ideal" modulators finds itself concisely rewritten as one particular case of this new theory.

Thao Nguyen obtained his PhD degree in Electrical Engineering at Columbia University in 1993. He joined the EEE Department of Hong Kong University of Science and Technology as an Assistant Professor from 1993 to 1997. He later became a member of technical staff at HP Laboratories in Palo Alto, CA, from 1998 to 1999. He has been an Associate Professor in the EE Department of The City College of New York since 1999. His research interest mainly focuses on the theoretical analysis of A/D and D/A conversion.

Prof. Arjang Hassibi
University of Texas at Austin

Date: 2:00pm, Friday, April 13, 2007
Place: EE Conference Room 1312 S.W. Mudd

Title:  Real-Time Integrated Microarrays: Fact or Fiction, Necessary or Cool?

The biotechnology industry has greatly matured in the in the past decade, a credit to recent scientific discoveries enabled by the new detection platforms. However, the performance of current detection platforms in biotechnology is still far from the ideal and thus there is a huge room for improvement. Their specificity (SNR), throughput, and dynamic range are even unacceptable for demanding applications such as point-of-care molecular diagnostics. Today, many of the researchers in electrical engineering and its related fields find this as a unique opportunity. Accordingly, we see a significant growth in the number of collaborative research projects between electrical engineers and biotechnologists to address the fundamental challenges of high-performance biological detection, i.e., biosensors.

The recent efforts in engineering, broadly defined, to address challenges of biotechnology have been mostly technology-driven. Unfortunately, it is very common to find many biotechnology-related engineering projects which attempt to “force” an existing engineering solution onto a biological application. Our goal in this talk is to look at the problem of detection (and biosensing) by using an application-driven approach, and examine the imperative and performance-limiting aspects of existing biosensor platforms. Our main focus will be on the affinity-based biosensor array technology (i.e., microarray platform) which is among the most powerful and widely used detection technologies in Genomics and Proteomics.

Initially in this talk we will examine the underlying physics of bio-molecular interactions which result in measurement uncertainty in affinity-based biosensors. Subsequently, we will introduce the concept of biological shot-noise and formulate the quantum-limited SNR of biosensors and microarrays, followed by the affects of non-specific binding (interference) and probe saturation (nonlinearity) on the limits of detection. The rest of this talk involves the methods which we have developed to increase the performance of microarrays. On the biochemical side, we demonstrate how real-time detection significantly increases the minimum-detection-level (MDL), while making probe saturation irrelevant. One the sensor implementation side, we demonstrate how standard CMOS processes can be used to integrate the microarray platform into a true system-on-a-chip (SoC) real-time integrated microarray system

Prof. Boris Murmann
Stanford University

Date: 2:00pm, Friday, March 9, 2007
Place: Interschool Lab -7th floor CEPSR

Title:  Digitally Assisted A/D Converters and Sensor Interface Circuits

Low-power data conversion has evolved as a key requirement in many modern electronic devices. Our work targets the development of a new class of ultra-low power "digitally assisted" ADCs. These converters are based on minimalistic, but power efficient analog sub-circuits and use digital processing for performance recovery and/or enhancement. Preliminary results presented in the first part of this talk indicate that this approach may deliver order-of-magnitude improvements in power efficiency. The second part of this presentation outlines our research activities in circuit design for MEMS and sensor interfaces. Specific highlights include a digitally assisted, low-drift MEMS accelerometer and MEMS-based resonators.

Boris Murmann received the Dipl.-Ing. (FH) degree in communications engineering from Fachhochschule Dieburg, Germany, in 1994 and the M.S. degree in electrical engineering from Santa Clara University, Santa Clara, CA, in 1999. In 2003, he received the Ph.D. degree in electrical engineering from the University of California at Berkeley, CA.  From 1994 to 1997, he was with Neutron Mikrolektronik GmbH, Hanau, Germany, where he developed low-power and smart-power ASICs in automotive CMOS
technology. During 2001 and 2002, he held internship positions with the High-Speed Converter Group at Analog Devices, Wilmington, MA. Since 2004, he is an Assistant Professor in the Department of Electrical Engineering, Stanford, CA. His research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. Dr. Murmann was a co-recipient of the Meritorious Paper Award at the 2005 US Government Microcircuit & Critical Technology Conference. He currently serves as a consultant to the Defensive Sciences Research Council (DSRC) and as a member of the International Solid-State-Circuits Conference (ISSCC) program committee.

Dr. Tierno
IBM T.J. Watson Research Center

Date: 2:00pm, Friday, February 23, 2007
Place: EE Conference Room 1312 S.W. Mudd

Title:  A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500MHz-to-8 GHz)
All Digital CMOS ADPLL in 65nm SOI

An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable PDI loop filter and features a third order delta sigma modulator. The DCO is a three stage, static inverter based ring oscillator programmable in 768 frequency steps. The ADPLL locks from 500 MHz to 8 GHz at 1.3V and 25°C, and from 90 MHz to 1.2 GHz at 0.5V and 100°C. The IC dissipates 8 mW/GHz at 1.2V and 1.6 mW/GHz at 0.5V. The synthesized 4 GHz clock has a period jitter of 0.7 ps rms, and long term jitter of 6 ps rms. The phase noise is -112 dBc/Hz at 4 GHz center frequency 10 MHz offset. The total circuit area is 200 um x 150 um.

Prof. Khaled Salama
Rensselaer Polytechnic Institute

Date: 2:30pm, Monday, February 26, 2007
Place: 414 - CEPSR

Title:  Integrated Biosensors

Over the past few years, we have witnessed a significant increase in research on biological systems by engineers for environmental and biomedical diagnostics. The research span a wide field ranging from biologically inspired systems (such as silicon retinas and cochleae), through electronic instrumentation of biological phenomena (such as DNA microarrays and chemical sensors) to man-machine interfaces (such as deep brain array stimulators and neuroprosthetic devices). Despite efforts to develop chips for biological assay detection, there continues to be a need to improve implementations of micro-scale detection and processing systems for further convenience, scaling and portability. These devices will lead to a significant cost-savings, throughput increases, and enable heretofore infeasible biological assays making “in the field” biological testing a reality. Thus infectious diseases can be detected rapidly and accurately onsite potentially averting the spread of illnesses or tainted foodstuffs.

We will present the design and implementation of monolithic and hybrid sensors using integrated circuits, particularly in CMOS. We will begin by providing the definitions and performance metrics of sensors. Subsequently, we will discuss the advantages and shortcomings of sensors built in silicon-based fabrication processes and examine, in detail, their integrated circuit topologies. Next, we will provide a comprehensive study of the design and analysis of CMOS integrated image sensors, integrated biosensors, and electronic backbone of MEMS hybrid sensors including silicon photodetectors; CCD and CMOS sensor architectures and circuits; affinity-based detection and biochemical transduction, integrated microarrays, biochips, and sensor SoCs.

Prof. Rinaldo Castello

University of Pavia Italy

Date: 2:00pm, Friday, February 9, 2007
Place: 414 - CEPSR

Title: Multimode Reconfigurable Wireless Terminals – a First Step Towards Software Defined Radio

Multimedia applications are driving wireless operators to add high-speed data services such as E-GPRS, UMTS and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode handsets that support a wide range of standards with different RF frequencies, signal bandwidth, modulation schemes, etc. This generates design challenges for the building blocks of the physical layer. In addition to the above protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice. Sharing and/or switching transceiver building blocks in these handsets is used to extend battery life and/or reduce cost. More specifically adaptive circuits that can reconfigure themselves within the handover time are used to enable a single receiver/transmitter covering all the different standards while ensuring seamless interoperability. This paper presents RF and analog base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required Quality of Service. Experimental measurements in a 0.13 um CMOS technology are presented and discussed.

Rinaldo Castello graduated from the University of Genova (summa cum laude) in 1977 and received the M.S. and the Ph. D. from the University of California, Berkeley, in ‘81 and ‘84. From ‘83 to ‘85 he was Visiting Assistant Professor at the University of California, Berkeley. In 1987 he joined the University of Pavia where he is now a Full Professor. He consulted for ST-Microelectronics, Milan, Italy up to 2005 and from ‘98 to ‘05 was the Scientific Director of a joint research centre between the University of Pavia and ST. Dr. Castello has been a member of the TPC of the European Solid State Circuit Conference (ESSCIRC) since 1987 and of the International Solid State Circuit Conference (ISSCC) from ‘92 to ‘04. He was Technical Chairman of ESSCIRC '91 and General Chairman of ESSCIRC ‘02, Associate Editor for Europe of the IEEE J. of Solid-State Circ. from '94 to '96 and Guest Editor of the July '92 special issue. Since 2000 he has been Distinguished Lecturer of the IEEE Solid State Circuit Society. Prof Castello was named one of the outstanding contributors for the first 50 years of the ISSCC and a co-recipient of the Best Student Paper Award at the 2005 Symposium on VLSI. He is a Fellow of the IEEE.

### Previous Seminars

 Fall     2006         Spring 2006          Fall     2005         Spring 2005
 Fall     2004         Spring 2004          Fall     2003         Spring 2003          Fall     2002
 Spring 2002         Fall     2001          Spring 2001         Fall     2000          Spring 2000

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