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Seminars Spring 2002

Mihai Banu

Senior Engineer, Agere Systems, New Jersey
Friday, April 26, 2:30 p.m.
Room: Interschool Lab

Wireless LANs


Wireless LANs based on the IEEE 802.11 standard have achieved wide customer acceptance in the enterprise environment. They are expected to continue to expand in popularity and become ubiquitous communication systems even in private and public places. This paper discusses the basics of the wireless LAN physical layer, focusing on radio tranceiver specifications and design options.

Sameer Sonkusale

Department of Electrical and Computer Engineering, University of Pennsylvania
Friday, April 12, 11:00am.
Room: Interschool Lab

Background Calibration Techniques for High Resolution Pipelined Analog-to-Digital Converters


Broadband wireless communication systems require high-speed, high-resolution Analog-to-Digital (A/D) Converters designed in digital CMOS process. One such application in cellular base stations requires the A/D Converter to digitize multiple channels at IF frequencies as high as 70 MHz with resolutions greater than 13 bits. Multi-bit Pipelined architecture for Analog-to-Digital conversion have been shown to provide high throughput at low power consumption. However practical realizations of these converters in digital CMOS process suffer from component mismatches, lower amplifier gains, offsets and charge injection errors, limiting their linearity to 8-10 bits of resolution at sampling rates in only tens of MHz. Existing Calibration Techniques to improve the resolution of the A/D Converters suffer from several drawbacks.

This talk will focus on background calibration techniques to improve the resolution of Pipelined Analog-to-Digital Converters in digital CMOS process. A general idea of the proposed technique is to adaptively correct for systematic errors in pipelined A/D converter using a least mean squares approach. The technique will be shown to achieve high linearity with minimal real estate and power consumption.

Shahriar Mirabbasi

Department of Electrical and Computer Engineering, University of Toronto
Monday, April 8, 11:00am.
Room: 414 Schapiro Building

Systems and Circuits for Integrated Wireless Receivers


The increasing demand for affordable and portable wireless communication systems has motivated substantial research into the realization of monolithic transceivers. The use of low-cost CMOS technology is of particular interest since it provides the possibility of integrating analog and digital circuitry on the same chip. Furthermore, the trend toward shifting more complexity from the analog to the digital domain in favor of robust and flexible performance, suggests more functionality should be implemented in the digital domain. Of particular interest is channel selection filtering, an essential function of any receiver. Also, the recent surge in high-data-rate wireless applications (e.g. wireless local area networks, multimedia) advocates the use of spectrally-efficient modulation schemes.

In this talk, we start with a review of the classical and modern receiver architectures suitable for a single-chip realization. Also, low-voltage realizations of RF building blocks (low-noise amplifier and mixer) will be discussed. Then, two research projects at the University of Toronto on a low-cost CMOS wireless video communication system are highlighted. First, Hierarchical QAM, a new DC-free spectrally-efficient modulation scheme is presented. Second, the realization of a delta-sigma decimation filter which also performs as a channel selection and approximate root-Nyquist pulse-shaping filter is described.

Barbara Chappell

Principal Engineer, Intel Corporation, Portland, Oregon
Friday, March 29, 2:30 p.m.
Room: Inter-School Lab

Challenges in Microprocessor Design


Challenges for ultra large-scale silicon products are summarized under five major headings: power-delivery, optimization, asychronization, re-use, and design-skills. Each is described with a broad brush and with illustrating examples from the viewpoint of the chip and circuit designer of microprocessor products. Synthesis systems are important tools for meeting these challenges. Briefly descriped is an advanced synthesis system for domino with 2Ghz silicon validation results. This is a workshop-style seminar with no distributed materials or recordings.

Sharad Malik

Department of Electrical Engineering, Princeton University
Friday, February 22, 2:30 p.m.
Room: 414 CESPR

Engineering an Efficient SAT Solver


Boolean Satisfiability is probably the most studied of combinatorial optimization/search problems. Significant effort has been devoted to trying to provide practical solutions to this problem for problem instances encountered in a range of applications in Electronic Design Automation (EDA), as well as in Artificial Intelligence (AI). This study has culminated in the development of several SAT packages, both proprietary and in the public domain (e.g. GRASP, SATO) which find significant use in both research and industry. Most existing complete solvers are variants of the Davis-Putnam (DP) search algorithm. In this talk I will describe the development of a new complete solver, Chaff, which achieves significant performance gains through careful engineering of all aspects of the search - especially a particularly efficient implementation of Boolean constraint propagation (BCP) and a novel low overhead decision strategy. Chaff has been able to obtain one to two orders of magnitude performance improvement on difficult SAT benchmarks in comparison with other solvers (DP or otherwise), including GRASP and SATO. This is joint work with Matt Moskewicz, Conor Madigan, Ying Zhao and Lintao Zhang.

Stephen Kosonocky

Manager of Low Power Circuits and Technology, IBM T. J. Watson Research Center
Friday, January 25, 2:30 p.m.
Room: 414 CESPR

Low Power Circuits and Technology for Wireless Digital Systems


As CMOS technology scales to deep submicron lengths, designers face new challenges in determining the proper balance of aggressive high performance devices and lower performance devices to optimize system power and performance for a given application. Determining this balance is crucial for battery powered handheld devices where device leakage and active power limit the available system performance. This talk will explore this question and describe research in developing low power communication systems which exploit the capabilities of advanced CMOS technology.

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