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Research   Seminars

Fall 2009

  Previous Seminars

     Dr. Carlos Galup Montoro
     Federal University of Santa Catarina

Date:  December 11th, 2:00pm,  414 CESPR/Schapiro
Topic:  CMOS analog design using all-region MOSFET modeling


This seminar on analog MOS circuits describes an accurate but simple MOS transistor model that reduces the distance between hand design and simulation results. In place of the common approach of furnishing separate analytical formulas for the strong and weak inversion regions of the MOS transistor, we provide simple formulas valid in all operating regions, including moderate inversion. This unified design approach, which is particularly suitable for analog design in advanced CMOS technologies, allows the insightful exploration of the design space. Large- and small-signal models of the MOSFET for low and high frequency, valid in all operating regions, are presented. The important concept of inversion level is developed and explicit expressions for all large- and small-signal parameters of transistors in terms of the inversion levels are provided. As means of demonstrating the usefulness of the all-region MOSFET model, we apply it to the design of elementary building blocks.

Speaker Biography

Dr. Carlos Galup-Montoro studied engineering sciences at the University of the Republic, Montevideo, Uruguay, and electronic engineering at the National Polytechnic School of Grenoble (INPG), France. He received an engineering degree in electronics in 1979 and a doctorate degree in 1982, both from INPG. From 1982 to 1989 he was with the University of São Paulo, Brazil, where he was engaged in junction field effect transistor (JFET) fabrication and analog circuit design. Since 1990, he has been with the Electrical Engineering Department, Federal University of Santa Catarina, Florianópolis, Brazil where he is now a professor. From August 1997 to February 1998 he was a research associate with the Analog Mixed SignalGroup, Texas A&M University. From August 2008 to July 2009 he was a visiting scholar at UC Berkeley. He is coauthor of the textbooks: "MOSFET Modeling for Circuit Analysis and Design", World Scientific, 2007 and "CMOS Analog Design Using All-Region MOSFET Modeling", Cambridge University Press, 2010

     Dr. Naresh Shanbhag
     University of Illinois at Urbana Champaign

Date:  November 20th, 2:00pm,  414 CESPR/Schapiro
Topic:  Communications-inspired System-Aware Mixed-signal IC Design


Moore's Law has been the driving force behind the exponential growth in the semiconductor industry for the past 40 years. Today, power and reliability challenges threaten the  continuation of Moore's Law. This talk will describe a communications-inspired design  paradigm for nanoscale SOCs, which has the potential to provide an elegant solution to  the power-reliability problem. This design paradigm views nanometer SOCs are miniature  communication networks, and exploits the principles of reliable information transfer  developed by communication system designers and information theorists over the past six decades to achieve energy-efficiency and reliability in nanoscale SOCs. Key elements of  this paradigm are the use of statistical signal processing principles, equalization and  error-control, for designing error-resilient on-chip computation, communication, storage, and mixed-signal analog front-ends.  The notions of stochastic computing and  system-assisted mixed-signal design emerge when the communications-inspired view is applied to computing and mixed-signal design, respectively. The talk will provide a  historical perspective, demonstrate examples of communications-inspired designs of on-chip sub-systems such as low-power filtering, video compression, PN-code acquisition, and on-chip and off-chip interconnect design, describe other on-going in the broader research community such as the Focus Center Research Program (FCRP). The seminar will  conclude with an invitation to signal processing and communication systems researchers to  collaborate actively with circuit designers in order ensure the future growth of semiconductors and their applications.

Speaker Biography


Naresh R. Shanbhag received his Ph.D. degree from the University of Minnesota in 1993 in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories at Murray Hill where he was the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. Since August 1995, he is with the Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory where he is presently a Professor. He was on a sabbatical leave of absence at the National Taiwan University in Fall 2007. His research interests are in the design of integrated circuits and systems for communications including low-power/high-performance VLSI architectures for error-control coding, equalization, as well as integrated circuit design. He has more than 150 publications in this area and holds four US patents. He is also a co-author of the research monograph Pipelined Adaptive Digital Filters published by Kluwer Academic Publishers in 1994. Since 2006, Dr. Shanbhag is leading the Alternative Computational Models research theme in the Gigascale Systems Research Center (GSRC), which sponsored by the Department of Defense (DOD) and Semiconductor Research Corporation (SRC) under their Focus Center Research Program (FCRP) since 2006.

Dr. Shanbhag became an IEEE Fellow in 2006, received the 2006 IEEE Journal of Solid-State Circuits Best Paper Award, the 2001 IEEE Transactions on VLSI Best Paper Award, the 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1999 Xerox Faculty Award, the Distinguished Lecturership from the IEEE Circuits and Systems Society in 1997, the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems Society. Dr. Shanbhag served as an Associate Editor for the IEEE Transaction on Circuits and Systems: Part II (97-99) and the IEEE Transactions on VLSI (99-02 and 09-present), respectively.  He is the technical program chair of the 2010 IEEE International Symposium on Low-Power Design (ISLPED), and is currently serving on the technical program committees of the International Solid-State Circuits Conference (ISSCC), the International Conference on Acoustics, Speech and Signal Processing (ICASSP), and others. In 2000, Dr. Shanbhag co-founded and served as the Chief Technology Officer of Intersymbol Communications, Inc., a venture-funded fabless semiconductor start-up that provided DSP-enhanced mixed-signal ICs for electronic dispersion compensation of OC-192 (10G) optical links. In 2007, Intersymbol Communications, Inc., was acquired by Finisar Corporation, Inc., where Dr. Shanbhag continues to provides counsel on technology strategy.  

     Dr. Ehsan Afshari

     Assistant Professor

Date:  October 30th, 2:00pm,  414 CESPR/Schapiro
Topic:  Circuit Design Beyond Transistor Limits


Waves are everywhere, from the distribution of cars on a highway to the wave patterns in the ocean. Intriguing phenomena in wave propagation, such as Soliton resonance, kink-antikink interaction, self-focusing, and Peakon generation can be used in many practical applications leading to novel architectures for signal processing and generation. These E/M based approaches could be particularly useful in the case of extremely high frequency (more than or around the transistor cut-off frequency) circuits and systems where the limited transistor cut-off frequency, maximum power efficiency, and breakdown voltage pose serious constraints on the use of conventional circuit techniques. To overcome the limitations of active devices in high frequency signal processing and generation, we propose a general class of solutions based on novel circuit topologies inspired by commonly used structures in electromagnetics, and more specifically optics. The proposed methodology is based on nonlinear and/or inhomogeneous one-dimensional (1D) transmission lines which we have successfully extended to two-dimensional transmission lattices. The principles behind these designs stem from the mathematical theory of linear and nonlinear wave propagation. By analyzing the models for the transmission lines/lattices, we are able to exploit the large body of theory to design circuits, demonstrating the narrowest reported pulse on silicon (<2ps), and for a single integrated-circuit silicon-based amplifier, the highest achieved center frequency of operation (85GHz) and the highest achieved power output (120mW) at this frequency. In addition, we will show how to generate a 300GHz signal in a 130nm CMOS process using the Doppler shift. We have also used this method to design a fast, low power, small foot-print ADC. Finally we will present how the same approach can be applied to realize ultra-fast computation systems (such as a sub-nanosecond Fourier and Hankel transformers in silicon) and other structures, leading to a new design discipline we like to call "Optotronics".

Speaker Biography


Prof. Ehsan Afshari was born in 1979. He received the B.Sc. degree in Electronics Engineering from the Sharif University of Technology, Tehran, Iran and the M.S. and Ph.D. degree in electrical engineering from the California Institute of Technology, Pasadena, in 2003, and 2006, respectively. In August 2006, he joined the faculty in Electrical and Computer Engineering at Cornell University.Prof. Afshari was awarded DARPA's Young Faculty Award in 2008 and Iran's Best Engineering Student award by the President of Iran in 2001. He is also the recipient of the best paper award in the Custom Integrated Circuits Conference (CICC), September 2003, the first place at Stanford-Berkeley-Caltech Inventors Challenge, March 2005, the best undergraduate paper award in Iranian Conference on Electrical Engineering, 1999, the recipient of the Silver Medal in the Physics Olympiad in 1997, and the recipient of the Award of Excellence in Engineering Education from Association of Professors and Scholars of Iranian Heritage (APSIH), May 2004.

        Dr. Jin Liu
        Assistant Professor
        University of Texas at Dallas 

Date:  October 16th, 2:00pm,  414 CESPR/Schapiro
Topic:  High-Speed Continuous-Time Equalization Techniques


In high-speed data communications with data rate over gigabit per second, a receiver equalizer has become an essential building block to mitigate the inter-symbol interference problem, which is due to limited bandwidth of low cost channel materials.  This talk first reviews existing equalization methods and then focuses on the discussion of continuous-time FIR filter equalizers.  Challenges of designing wide-bandwidth delay line and solutions will be discussed.  Several IC designs with improved data rates from 1Gb/s to 10Gb/s will be reviewed.  Also discussed are adaptation methods for such FIR equalizers

Speaker Biography


Dr. Jin Liu received the B.S. degree in Electronics and Information Systems from Zhongshan University in P.R. China in 1992, the M.S. degree in Electrical and Computer Engineering from University of Houston in 1995, and the Ph.D. degree in Electrical and Computer Engineering from Georgia Institute of Technology in 1999.  She joined the University of Texas at Dallas as an assistant professor in 1999 and is currently an associate professor at the same university.  She was an associate editor of IEEE Transactions on Circuits and Systems II from 2004-2006.

Her research interests are high-speed communication circuits, sensor interface circuits, and system integration/miniaturization Current projects include: adaptive equalization and clock/data recovery circuits for high-speed data communications; low-power CMOS motion detection imagers; rad-hard sensor interface circuits for satellite; power and data transmission circuits for battery-less and wireless sensors; and high-speed A/D converters.

     Dr. Krishnaswamy Nagaraj
     Distinguished Member of Technical Staff, Wireless Terminals Business Unit
     Texas  Instruments 

Date:  October 2nd, 11:00am, Interschool Lab. (7th Floor CESPR/Schapiro)  Directions
Topic:  Digital Phase-Locked Loops Open Up New Avenues for Clock Generation in SOCs

This seminar is part of the distinguished lecture series sponsored by the New York chapter of the IEEE EDS/SSCS, please visit


Phase lock loops (PLLs) are an indispensable part of today's systems-on-chip (SOCs). They are used extensively for generating clocks for digital signal processing blocks, as well as carriers for RF receive/transmit blocks. Traditional implementations of PLLs have been analog in nature. With the trend towards system integration using digital CMOS technologies, a new class of PLLs, namely, Digital Phase Lock Loops (DPLLs) has emerged recently. DPLLs  offer several advantages, including the elimination of passive components, flexibility and programmability and the possibility of applying sophisticated DSP techniques to improve performance and reduce power consumption. This talk will present an overview of recent developments in DPLL architectures and circuits.

Speaker Biography

Krishnaswamy Nagaraj is presently a Distinguished Member of Technical Staff with Texas Instruments in Dallas, where he is engaged in the development of low power, high performance circuits and systems in nanometer CMOS technologies. Previously, he was a Distinguished Member of Technical Staff at the Bell Laboratories in Murray Hill, New Jersey. He has served as an Associate Editor of the IEEE Transactions on Circuits and Systems Part II, IEEE Journal of Solid State Circuits and as the Editor-in-Chief of the IEEE Journal of Solid State Circuits. He was an Adjunct Associate Professor at the University of Pennsylvania from 1996 to 2003. He is a Fellow of the IEEE.

      Dr. Ulrich L. Rohde
      Synergy Microwave Corporation

Date:  September 11th, 2:00pm, 414 CESPR/Schapiro
Topic:  Modern Ultra-Low-Noise Microwave Transistor Oscillator Design


This seminar will cover the design of microwave oscillators based on bipolar transistors, a topic that has always been considered a black art. We will give a thorough presentation of their design. We will look at both the frequency and time domain approaches, and use nonlinear S-parameters to determine the starting and sustaining conditions. These determine the phase noise. It is possible to use this technique for MOS transistors and also planar multiple resonators; the use of "tricky" circuits will further improve the phase noise. The technique presented may also be applicable for IC designs.

Speaker Biography

Ulrich L. Rohde, Ph.D., Dr.-Ing., IEEE fellow, is a professor of microwave and RF technology at the Technical University (TU) of Cottbus, Germany; Chairman of Synergy Microwave Corporation, Paterson, NJ; partner of Rohde & Schwarz, Munich, Germany; and a past member of the Innovations for High Performance Microelectronics (IHP) Scientific Advisory Council, Frankfurt Oder, Germany.  He was previously President of Compact Software, Inc., and a member of the Board of Directors of Ansoft Corporation.  He has published 8 books and more than 100 scientific papers.  His main interests are communications systems and circuits, specifically low-noise oscillators and high-performance mixers and synthesizers for microwave applications. He holds more than one dozen patents in this area and several patent applications are in the processing stage. 

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