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Seminars Fall 2004

Edgar Sanchez-Sinencio, TI/J. Kilby Chair Professor

Texas A&M University
Date: Monday, December 13th, 2004, 2:30pm
Place: Interschool Lab, 7th Floor, Schapiro Building (CEPSR)

Title: A High Dynamic Range 2.5 GHz Fourth-Order Tunable LC 0.5 um CMOS Bandpass Filter


Among different topologies for RF bandpass filters, active LC type filter is a good candidate as it can provide a high quality factor (Q) bandpass transfer function with significant reduced power consumption and higher dynamic range in comparison to Gm-C type filters. Mutually coupled inductors is an attractive way to realize impedance transformation and more immune to process variations. Regardless of the coupling mechanism between the resonators, losses associated with the on-chip reactive components change the center frequency and loaded quality factor of the filter. An enhanced high dynamic range CMOS fourth-order LC type RF bandpass filter is presented. The magnetically coupled resonators are emulated based on the electric coupling between two individual inductors. Coupling coefficient can be changed to tune the bandwidth of the filter. The proposed electrically coupled resonators scheme is not based on a resistive sensor path to couple the two resonators. This reduces the noise and increases significantly the dynamic range of the filter. The filter has been implemented in AMI 0.5 um CMOS process and occupies an area of 0.15 mm2. The prototype operates at a center frequency of 2.5GHz with a bandwidth of 92MHz, and a passband gain of 11dB and 25dB of image attenuation for an IF frequency of 100MHz. It draws less than 16mA current from a single 2.7-V supply. The measured IM3 is -38dBm for two tones applied at 2.5GHz and 2.51GHz with equal amplitudes of -38dBm. The measured 1-dB output compression point is -32dBm. The measured output noise is -84dBm in a 100MHz filter's bandwidth which results in a 52dB dynamic range and 32dB noise figure.

Mihai Banu, Vladimir Prodanov, Kent Smith

Analog Products Division, Agere Systems, Allentown, PA
Date: Friday, December 3rd, 2004, 2:30pm
Place: Room 414, 4th Floor, Schapiro Building (CEPSR)

Title: A Differential Scheme for LDMOS Power Transistor Class-AB Biasing Using On-Chip Transconductance Replicas


We describe a new principle for biasing LDMOS class-AB power amplifiers, using on-chip gm replicas for setting and maintaining a constant gm ratio over temperature and process variations. The conventional constant quiescent drain current condition is automatically met over temperature and improved linearity statistical spread is achieved over transistor fabrication variations. Fully differential operation ensures insensitivity to RF leakage.

Rahul Sarpeshkar

Massachusetts Institute of Technology
Date: Monday, November 29th, 2004, 2:30pm
Place: Room 414, 4th Floor, Schapiro Building (CEPSR)

Title: Energy-Efficient Bioelectronics


Biomedical systems such as fully implanted prosthetics for the deaf, blind or paralyzed require decades of operation on a small battery. Neurobiological systems use impressively few resources of energy, space, and time to solve complex sensory and sensorimotor tasks and provide inspiration for energy efficient electronic design. First, I will describe research on high-performance, ultra-low-power silicon chips inspired by the biological cochlea. Such chips have applications in various domains where spectral analysis in noisy environments is essential such as in bionic implants for the deaf or in speech recognition. I will demonstrate an application from this research, an all-analog soon-to-go-commercial bionic ear processor with such low power consumption that a conventional A-D-then-DSP technique will not be able to beat it two decades in the future. This processor will enable 30 year operation on a small 100mAh battery in fully implanted cochlear implants of the future. Then, I will outline applications of bioelectronics to some other domains such as novel companding processors for speech recognition in noise, RF cochleas for ultra wide band radios, MEMS cochleas, analog memory for adaptive systems, RF ID tags, machine vision systems and robotics.

Azita Emami-Neyestanak

IBM T.J.Watson Research Center
Date: Friday, November 19th, 2004, 2:30pm
Place: Interschool Lab, 7th Floor, Schapiro Building (CEPSR)

Title: Transceiver Design for High Speed Optical Interconnects


The increasing speed of on-chip data processing and computation create a growing demand for high-bandwidth input and output (IO) to VLSI circuits. However, increasing the bandwidth of electrical signaling with the same rate is becoming very challenging. The possibility of using optics for interconnection at short distances has been recently a subject of considerable research and analysis. A very promising design platform is to hybrid integrate dense arrays of optical devices (lasers, modulators and detectors) with commercial electronic circuits to establish a very high data rate, parallel link for chip-to-chip interconnection. Such a system requires receiver and transmitter circuitry that is very small and has low power consumption. This talk describes the design and implementation of CMOS transceivers suitable for parallel optical interconnects with flip-chip-bonded optical devices. The receiver front-end uses a novel double sampling/integrating scheme with 1:5 demultiplexing to avoid having to build a transimpedance amplifier that runs at the bit rate. In this design the optically generated current is integrated onto the parasitic capacitor of the input node and voltage-samples are compared for data recovery. Moreover rather than using the standard 2x oversampled approach for clock recovery, this receiver uses a new baud-rate CDR based only on data samples, to reduce both complexity and power consumption. Our transceiver test chip achieves data rates as high as 5Gb/s and consumes less than 145mW of power per link in a 0.25 um CMOS technology. At the end, scaling to future technologies and potential extension of these techniques for future research will be briefly discussed.

Brian Floyd

IBM T.J. Watson Research Center
Date: Friday October 29th, 2004, 2:30pm
Place: Room 414, Schapiro Building (CEPSR)

Title: Millimeter-Wave Circuits and Systems: An Emerging Opportunity for SiGe


SiGe technology has advanced to the point that the devices can now operate at millimeter-wave frequencies. Silicon's economy of scale promises high levels of integration and thereby reduced system cost, which in turn could open up new market opportunities. Promising applications include automotive radar at 77 GHz and near Gbps personal-area networks and point-to-point links at 60 GHz. This talk will provide an overview of millimeter-wave applications and design methodologies, and then focus on 60-GHz transceiver circuits which have been successfully realized in a 0.12-um SiGe bipolar technology. Some of the results include a 60-GHz LNA with 15-dB gain and 4.5-dB NF, a 60-GHz direct-downconverter with 18-dB gain and 13-dB NF, a 60-GHz power amplifier with +11.2-dBm P1dB and 4.3% PAE, and a 67-GHz VCO with -98 dBc/Hz phase noise at 1-MHz offset. In addition to the circuit results, the talk will also highlight antenna, package, and passive component development for millimeter-wave.

Gert Cauwenberghs

Adaptive Microsystems Laboratory, Johns Hopkins University
Date: Friday October 15th, 2004, 2:30pm
Place: Room 827, S.W.Mudd Building

Title: Microscale Integrated Acoustic Source Separation and Localization


I will present mixed-signal VLSI adaptive microsystems interfacing with miniature microphone arrays that perform acoustic source separation and localization at microwatts of power, for use in intelligent hearing aids and acoustic surveillance. Analog gradient sensing of the broadband traveling wave field at sub-wavelength scale across a planar array of sensors yields linearly mixed instantaneous observations of multiple sources, blindly separated and 3-D localized using independent component analysis. The principle extends directly to the radio-frequency domain for low-power separation and localization of multiple broadband users in wireless networks.
This is a joint work with Milutin Stanacevic and Abdullah Celik.

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