The problem of energy optimization in multi-core systems (such as single-chip multiprocessors) where the individual energy demands of various processing elements are governed by instantaneous workload requirements is well defined in literature. The significance of the problem is underlined by the increasing prominence of multi-core systems that must operate under strict power/energy budget constraints, both in mobile applications and in cases where special cooling arrangements can be very expensive. A range of solutions have been proposed over the last few years, which are mostly based on static, off-line calculation of a limited set of operating points in the form of optimum voltage and frequency assignments, that are subsequently chosen according to actual demands. Still, to our best knowledge, none of these studies have demonstrated an on-line solution to complex, multi-variable energy optimization problem which allows dynamic adjustment of individual operating frequencies and supply voltages of multiple processing elements. This work presents the design and silicon implementation of an analog-based energy optimizer unit, which is capable of dynamically adjusting power supply and clock frequencies of multiple embedded cores, tailored to the instantaneous workload information (computational task) and fully adaptive to variations in process and temperature.

Our approach borrows from the basic principles of analog computation to continuously optimize the system-wide energy dissipation of multiple processing elements, converging on the global minima of the constrained optimization problem which are represented as stable operating points of a simple feedback loop. It is already well known that stable, approximate solutions of multi- variable optimization problems (such as gradient descent) can be obtained by using very compact analog circuits, e.g. resistive networks. The analogy between the energy minimization problem under timing constraints in a general task graph and the power minimization problem under Kirchhoff's current law constraints in an equivalent resistive network is exploited. The implementation of the on-line analog optimizer is then discussed. The realization of the blocks composing the system architecture is described, and circuit design issues are studied thoroughly.

This talk presents wireless technologies that can achieve high data rates (0.1-5 Gb/s) and are amenable to CMOS integration. The first technology discussed uses multiple antennas (MIMO) and spatial multiplexing to obtain high data rates by re-using a limited RF bandwidth. In spatial multiplexing MIMO, independent data streams are transmitted from the different transmit antennas. These data streams merge in the wireless channel but the receiver can still separate them by using advanced DSP techniques. The talk discusses the implications of MIMO processing to the RFIC design. It is shown that crosstalk between the multiple transceivers residing on the same die can degrade the MIMO performance and has to be carefully minimized, especially when power amplifiers are integrated on-die. A 5GHz 2x2 MIMO prototype has been fabricated and tested to demonstrate these ideas. The transceiver includes linearized integrated power amplifiers that deliver a 1-dB compression point power of 20.5dBm. The MIMO transceiver achieves a data rate of 108Mb/s, which is double what conventional single-antenna WLAN technology can achieve within the same RF bandwidth, demonstrating the spectral efficiency advantage of MIMO spatial multiplexing. Even higher data rates can be achieved by using abundant, underutilized RF bandwidth available at mm-wave frequencies (e.g. 60GHz). Wireless communications at mm-wave frequencies present severe challenges due to increased path loss, deteriorating transistor performance, and packaging complications. These issues might be offset by the large RF bandwidths available and the small antenna size that might allow the deployment of antenna arrays to help restore the performance of the overall system. The challenges and opportunities of mm-wave transceivers are reviewed and some first experimental results are reported.

A 0.13-um SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject LNA, RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, PLL, and frequency tripler. It achieves a 6-dB NF, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a PA, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P1dB of 10 to 12 dBm, Psat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s and 10 m has been demonstrated. Wireless transmission of un-compressed high-definition digital video at 2 Gb/s has also recently been achieved.