Dr. Aleksander Dec & Dr. Ken Suyama
Epoch Microelectronics
Date: Friday, March 11, 2005, 2:30pm
Place: 414 CEPSR
Title:
Integrated VCOs for Cellular Phone Applications
Abstract:
Recent
trend for RF transceivers for high volume market such as cellular
phone market is moving toward complete integration of RF front-end
circuit and some part of baseband blocks in order to lower the cost
of manufacturing. External component count must be lowered. This
means that VCOs, loop filters, and many passive elements such as chip
capacitors must be integrated.
This
presentation illuminates various aspects of integrating VCOs for
GSM/DCS cellular phone applications although other applications such
as WLANs, tuners, and etc have very similar set of design issues.
Publications often emphasize phase noise and power as the main figure
of merit. However, there are many other design issues in real
product design that make trade-off equations complicated. For
example, an integrated VCO often requires (1) wide tuning range for
multi-band coverage (triple or quad band for GSM/DCS), (2) Kv (gain
of VCO) linearity, (3) low phase noise, (4) low power, (5) low supply
pushing, (6) low sensitivity to temperature variations, (7) low
sensitivity to process variations for better yield, (8) low noise
floor design for output buffers (for TXVCOs used in OPLL), (9) small
area (large passives are sin!), and (10) other considerations like
pulling and coupling.
Three
integrated VCOs (IFVCO, TXVCO, and RFVCO) are presented to show
design strategies to address the above mentioned trade-offs.
Dr. Vincent Leung
IBM T.J. Watson Research Center
Date: Friday, April 1, 2005, 2:30pm
Place: Interschool Lab (7th Floor CEPSR)
Title:
Digital-IF SiGe BiCMOS Transmitter IC for 3G WCDMA Handset Application
Abstract:
This talk presents the design and the experimental results of an
analog/ RF front-end transmitter IC (TxIC) developed for the next
generation (3G) WCDMA mobile phone applications. Implemented in IBM's
0.25um SiGe BiCMOS process, this TxIC chip achieves high integration
level and low power consumption through a combination of architecture
and circuit innovations.
Based on a digital-IF heterodyne scheme, it eliminates the costly and
bulky IF SAW filter by adopting an optimized frequency planning and a
special-purpose high-order-hold D/A conversion method. The TxIC
features a low-power high-speed DAC designed to drive a dominantly
capacitive load. For the up-conversion mixer and the RF amplifier,
adaptive biases are designed to minimize the quiescent power
consumption and to provide current boost only when needed. The TxIC
achieves <1% EVM. It consumes 180mW (3V supply) for the maximum
output power of +5dBm, and reduces to 120mW during power backoff.
(This work was conducted at University of California, San Diego, under
the joint supervision of Prof. Larry Larson and Dr. Prasad Gudem of
Qualcomm.)
Dr. Eduard Sackinger
Conexant
Date: Friday, April 15, 2005, 2:30pm
Place: Interschool Lab (7th Floor CEPSR)
Title: An
Integrated CMOS 2.5Gb/s Front-End for SONET Applications.
Abstract:
In the first part of this presentation, I will describe the design and
experimental results of a 3GHz, 32dB limiting amplifier in 0.25um CMOS
using low voltage-drop active inductors and inversely scaled stages. In
the second part, I will describe the design and experimental results of
a 2.5Gb/s CMOS receiver chip which combines the above limiting
amplifier with a CDR and 1:4 DMUX.
Prof. Ralph Etienne-Cummings
Department of Electrical and Computer Engineering, Johns Hopkins
University
Date: Friday, April 22, 2005, 2:30pm
Place: Interschool Lab (7th Floor CEPSR)
Title: Neuromorphic Vision Chips:
Bioloigcally Inspired Cameras and Their Application
Abstract:
Embedded image processing on the focal plane promises high image signal
quality and fast, compact and low-power information extraction for
machine vision applications. Over the past decade, the promise of
improved signal quality has been achieved, and we are now able to buy
cheap ~60dB CMOS high-resolution imagers. The goal of fast, compact and
low-power information extraction is, however, still elusive. Problems
with inefficient chip area usage, incompatible algorithms and high
power consumption, typically high speed digital, have limited the
success on this front.
We have developed a technique that attempts to provide all these
promises using digitally programmable analog computation and
Computation-On-Readout (COR). Our approach remains compatible with
standard computer vision interfaces by preserving the image resolution
and scanning format, while in parallel extracting various
spatiotemporal features from images. Furthermore, our systems perform
greater than 10 GOPS/mW, ~6 bits of resolution, at many thousands of
frames per second. Because of the high performance, low-power and
compact sizes of these neuromorphic vision chips, they
can be easily used as the visual sensor for mobile robots.
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