(Based on Bob's work to be presented at ISSCC 2008)

This talk presents a pipelined analog to digital converter (ADC) operating from a 0.5-V supply voltage. The ADC uses true low-voltage design techniques that do not require any on-chip supply or clock voltage boosting. The switch OFF leakage in the sampling circuit is suppressed using a cascaded sampling technique. A front-end signal-path sample-and-hold amplifier (SHA) is avoided by using a coarse auxiliary sample and hold (S/H) for the sub-ADC, and by synchronizing the sub-ADC and pipeline-stage sampling circuit. A 0.5-V operational transconductance amplifier is presented that provides inter-stage amplification with an 8-bit performance for the pipelined ADC operating at 10 Msps. The chip was fabricated on a standard 90nm CMOS technology and measures 1.2 mm by 1.2 mm. The prototype chip has 8 identical stages and stage scaling was not used. It consumes 2.4 mW for 10-Msps operation. Measured peak SNDR is 48.1 dB and peak SFDR is 57.2 dB for a full-scale sinusoidal input. Maximal integral nonlinearity (INL) and differential nonlinearity (DNL) are 1.19 and 0.55 LSB respectively.

This talk presents an extension of instantaneous companding (compressing and expanding) to digital signal processors (DSPs). Companding has been used for many years in non-dynamical channels, but the dynamical nature of DSPs causes output distortion in standard implementations of companding,
where a compressor and expander are used at the input and output, respectively, without additionally modifying the DSP. In contrast, the proposed technique combines input compression, output expansion, and application of nonlinear functions internal to the DSP, all in a manner transparent to the input-output characteristics of the DSP and its A/D interfaces, thus eliminating distortion in the final
analog output. As a result, all the signals involved span most of the available bits, resulting in significant improvement in quantization errors and signal-to-noise-plus-distortion ratios over a large input range. The theory is supported by simulation and subjective listening tests.

Recent developments on wireless and wireline communications have pushed the operation freuqency toward tens of  gigahertz. This talk presents novel high-speed techniques for  different applications as well  as their silicon realizations, comprising a 75-GHz PLL, a 20-Gb/s burst-mode CDR, and a 60-GHz RF front end. Future design  trends for high-speed circuits are also included.

Bio: Jri Lee received the B.Sc. degree in electrical engineering  from National Taiwan University (NTU), Taipei, Taiwan in 1995, and  the M.S. and Ph.D. degrees in electrical engineering from the  University of California, Los Angeles (UCLA), both in 2003. His current research interests  include high-speed wireless and wireline transceivers, phase-locked  loops, and data converters.
He has been an Assistant Professor in electrical engineering  at National Taiwan University since 2004. Prior to that, he had  military service for 2 years and worked in the industry/research  institute for 3 years. Dr. Lee received the Beatrice Winner Award  for Editorial Excellence at the 2007 ISSCC, and NTU Outstanding  Teaching Award in 2006. He is currently serving in the technical  program committees of International Solid-State Circuits Conference (ISSCC) and Asian Solid-State Circuits Conference (A-SSCC).