Seminars Fall 2001

Abstract:

Since power consumption is now a first-class design contraint, "power-awareness" is a necessary aspect of modeling and design. This is true for all stages of design and at all levels of abstraction. In this talk, we will focus on power-aware design at the microarchitecture definition stage. We start by presenting our group's work on early-stage, workload-driven power-performance modeling. Augmenting the current architectural simulation tools to include energy behavior of the unit-level components is the first step in conducting research in this emerging new area. We also describe the model validation methods that we are pursuing to understand the relative and absolute accuracy implications of such early-stage models. In the second part of the talk, we describe some of the specific power-aware microarchitecture ideas that we have studied. We present simulation-based and analytical results to understand: (a) the power-performance efficiency benefits of dynamic adaptation and throttling of on-chip computing resources: e.g. issue queues and instruction fetch bandwidth; (b) the fundamental limits of scaling within a given microarchitectural paradigm: e.g. super scalar, with and without simultaneous multithreading (SMT) as well as chip multiprocessing. We also address the microarchitectural support issues for coarse- and fine-grain clock gating as well as Vdd (power) gating; and, we project the effect of such "gating" methods on power-performance scalability.

Abstract:

Designing CMOS devices for high-performance servers has always been a challenge. Scaling devices to keep up with the higher performance Moore's Law demands from each generation has already forced gate lengths below 0.1um and gate oxides below 1.5nm, so ever more creative methods of technology improvement -- beyond simple scaling -- are needed. To face this challenge, IBM has been a leader in introducing many new materials, such as Cu wires and SiLK(TM) low-K intermetal dielectric, and new technologies, such as SOI and strained-Si. This talk will cover many of these technologies, and how they affect the device designers task, particularly focusing on SOI CMOS design. In addition, the rise of the internet, high-speed networking, and mobile computing have introduced a new set of requirements for semiconductor technologies. Various extensions of SOI CMOS that attempt to meet these needs, such as adding devices optimized for RF or low-power performance, as well as embedding DRAM into SOI logic processes, will also be touched on briefly.

Abstract:

This presentation reviews recent advances in SOI circuit design for high-performance digital applications with particular emphasis on the circuit / design issues resulting from the unique SOI device structure. The technology / device choices / requirements and design challenges are highlighted. Unique design aspects for partially-depleted SOI , such as parasitic bipolar effect, hysteretic Vt variation, temperature dependence, and scaling implications, are addressed. Circuit techniques to improve the noise immunity and performance, and design methodology to handle and contain the hysteretic Vt variation are discussed.