|
|
Spring 2016: Upcoming Seminars
|
|
Title:
The Challenges of Implementing Broadband ADCs
Speaker:
Dr. Leonard Dauphinee
Date:
Friday, Apr. 15th, 2pm, 414 CEPSR
Title:
Energy Efficient Circuit Technologies for the sub-14nm Era: Challenges and Opportunities
Speaker:
Dr. Ram Krishnamurthy
Date:
Monday, May 2nd, 2pm, 750 CEPSR
|
|
|
|
Prof. Salvatore Levantino
Politecnico di Milano
Date:
Friday, Jan. 29th, 10:00am-11:00am
Location:
750 CEPSR
|
Mostly Digital Phase-Locked Loops
Abstract:
This talk will discuss the fundamentals of digital phase-locked loops and analyze the mechanisms of generation of limit cycles, which manifest themselves as spurious tones at the output. Then, we will compare two different quantization strategies and develop practical design examples showing how to set loop parameters and optimize phase noise and jitter. The second part of the tutorial will be devoted to fractional-N synthesis, in which quantization and nonlinearity add new sources of spurious tones: We will review the different design techniques which help mitigate such impairments.
Biography:
Salvatore Levantino is Associate Professor of Electrical Engineering at Politecnico di Milano, Milan, Italy. His research includes wireless transceivers, frequency synthesizers, and data converters. Author of more than 80 papers on IEEE journals and conferences and the book "Integrated Frequency Synthesizers for Wireless Systems" published by CUP in 2007. He is associate Editor of IEEE TCAS-I and member of the Steering Committee for the IEEE RFIC Symposium.
|
|
Prof. Nagendra Krishnapura
IIT Madras
Date:
Thursday, Feb. 4th, 11:00am-12:00pm
Location:
414 CEPSR
|
Memoryless Analog-to-Digital Conversion Using Delta-Sigma Modulators Without Reset
Abstract:
Delta-Sigma architectures are usually the best choice for high resolution analog-to-digital converters. But when the input is multiplexed from a number of inputs, delta-sigma ADCs cannot be used directly. The memory in the modulator and the decimation filter results in inter-sample interference. To eliminate this, the conversion cycle has to be made long enough for the impulse response of the modulator and decimator to die out before applying the next sample. This results in a substantially lower sampling rate than when the Delta-Sigma ADC is used continuously. Alternatively, the modulator and decimation filter can be reset to realize an incremental delta-sigma modulator. In this case, there is an SNR penalty since the filtering less effective. In this work, it is shown that memoryless analog-to-digital conversion using $\Delta\Sigma$ modulators is possible without resetting the modulator or decimation filters. This is done by constraining the combined signal transfer function for the modulator and a decimation filter to satisfy Nyquist intersymbol interference criterion. This architecture enables memoryless operation over the entire signal bandwidth of the Delta-Sigma modulator which is significantly higher than the bandwidth in incremental architectures in which the modulator is reset. A two-channel ADC with sampling rate of fs/64 per channel is built using a third order 32 times oversampled switched-capacitor modulator. The prototype in 0.18um CMOS occupies 2.1mmsq. At 64MHz sampling rate for the DSM, the standalone modulator consumes 25mW and has a DR/SNRmax/SNDRmax of 85/82/80.3 dB. The sample-and-hold required for multi-channel operation consumes 20 mW. In two-channel mode, with 1 MHz sampling rate per channel, the DR/SNRmax/SNDRmax of 80/76/75 dB. The crosstalk between channels is less than 85 dB. The total power consumption for two channels is 45 mW.
Biography:
Nagendra Krishnapura obtained his BTech from the Indian Institute of Technology, Madras, India and his PhD from Columbia University, New York. He has worked as an analog design engineer at Celight, Multilink, and Vitesse semiconductor. He has taught analog circuit design courses at Columbia University as an adjunct faculty. He is currently an associate professor at the Indian Institute of Technology, Madras. His interests are analog and RF circuit design and analog signal processing.
|
|
Prof. Kumar Lakshmikumar
Cisco Systems, Inc.
Date:
Friday, Feb. 26th, 2:00pm-4:00pm
Location:
750 CEPSR
|
2-hr Short Course: Clock and Data Recovery Techniques for Optical Communication Systems
Abstract:
Clock and Data Recovery (CDR) is a key function in a communication system. We begin this part of the course with a review of the fundamentals of CDR in Non-Return-to-Zero (NRZ) serial links. System level metrics like jitter-tolerance, jitter-transfer and jitter-generation are introduced to evaluate the performance of a CDR. Several CDR architectures are discussed. Their advantages and drawbacks specifically for high-speed optical systems are compared. Many optical systems require a reference-less CDR. Various techniques to extract frequency from the incoming data are explained in detail. Linear and bang-bang phase detectors at full-rate are introduced. Sub-rate structures that ease the speed requirements of the circuits are also described.
Biography:
Kadaba R. (Kumar) Lakshmikumar received his B.E. and M.E. degrees in Electrical Communication Engineering from the Indian Institute of Science, Bangalore, India, and Ph.D. degree in Electrical Engineering from Carleton University, Ottawa, Canada. He did pioneering work in the area of modeling mismatch in MOS devices for his doctoral work. The standard deviation of mismatch was shown to be inversely proportional to the square-root of the channel area. His paper in the December 1986 issue of the IEEE Journal of Solid-State Circuits is among the top 20 cited publications of the journal between 1968 and 1992.(http://www.ieee.org/organizations/pubs/newsletters/sscs/oct02/TopArticles.html.)
Lakshmikumar has made lasting contributions to the field of IC design through his leadership in identifying and solving technically challenging problems. He presented a tutorial titled ¡°PLL Design in Nanometer CMOS¡± at ISSCC 2010. The tutorial (http://sscs.ieee.org/tutorials-on-line/2010-issccshort-courses-and-tutorials/426-isscc-2010-tutorial-pll-design-in-nanometer-cmos.html) illustrates design techniques for overcoming large variability, low supply voltage and high leakage. In 2015, he presented a short course, ¡°Clock and Data Recovery Techniques for Optical Communication Systems¡± at CSICS.
He has held senior engineering positions at Bell Labs, Multilink and Conexant Systems. Currently he is heading the analog design group at Cisco Systems¡¯ Silicon Photonics division in Allentown, PA. He has served on the Technical Program Committees of IEEE Custom Integrated Circuits Conference and IEEE International Solid State Circuits Conference and Compound Semiconductor Integrated Circuits Symposium. He is an associate editor of the IEEE Journal of Solid-State Circuits. He has mentored a number of graduate students and serves as an external examiner for Ph.D. candidates. Lakshmikumar is a Fellow of IEEE.
|
|
Prof. Azita Emami
CalTech
Date:
Monday, Feb. 29th, 3:00pm-4:00pm
Location:
750 CEPSR
|
Holistic Energy-Efficient Design in Optical Interconnects
Abstract:
The scalability of CMOS technology has driven computation into a diverse range of applications across the power consumption, performance and size spectra. Communication is a necessary adjunct to computation, and whether in the context of high-performance computing, mobile devices or biomedical implants, chip-to-chip communication can take up a significant portion of the overall system power budget. Today Data Center and High Performance Computing (HPC) performance is increasingly limited by interconnection bandwidth. Maintaining continued aggregate bandwidth growth without overwhelming the power budget for these large scale computing systems and data centers is paramount. The historic power efficiency gains via CMOS technology scaling for such interconnects have rolled off over the past decade, and new low-cost approaches are necessary. In this talk a number of promising solutions including Silicon-Photonic-based interconnects that can overcome these challenges will be discussed. In particular effective co-design of electronics and photonics as a holistic approach for reducing the total power consumption and enhancing the performance of the link will be presented.
Biography:
Azita Emami received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1999 and 2004 respectively. She received her B.S. degree from Sharif University of Technology in 1996. Professor Emami joined IBM T. J. Watson Research Center in 2004 as a research staff member in the Communication Technologies Department. From Fall 2006 to Summer 2007, she was an Assistant Professor of Electrical Engineering at Columbia University. In 2007, she joined Caltech, where she is now a Professor of Electrical Engineering and Medical Engineering. She also serves as the deputy chair of division of Engineering and Applied Sciences at Caltech. Her current research interests include mixed-signal integrated circuits and systems, high-speed on-chip and chip-to-chip interconnects, system and circuit design solutions for highly-scaled CMOS technologies, wearable and implantable devices for neural recording, stimulation, and efficient drug delivery. |
|
Dr. Len Dauphinee
MaxLinear, inc.
Date:
Friday, Apr. 15th, 2:00pm-3:00pm
Location:
414 CEPSR
|
The Challenges of Implementing Broadband ADCs
Abstract:
The exploding demand for high speed wired and wireless data networks has radically changed today's data RF transceivers and modems. Gigahertz bandwidths require broadband ADC architectures. Although initial ideas for this architecture was filed as a patent in 2003, it took another 9 years before it would become a reality. This seminar talks about some of the challenges of implementing broadband ADCs. The talk also describes several applications of this technology and how it has transformed the data communications industry.
Biography:
As Vice President and Chief Technology Officer, Len is responsible for the technology of MaxLinear's Broadband business which generated over $300 million in revenue last year. Len joined MaxLinear in 2012 as Vice President of Systems Engineering. In this role, he was responsible for hardware and software development across all products lines. Previous to MaxLinear, he was at Broadcom since 1998 and led broadband RFIC design for MoCA, satellite TV, cable modem, cable STB, terrestrial TV, and microwave backhaul products. He received a Ph.D. in Electronics from Carleton University and is a named inventor on over 60 issued or filed U.S. patents.
|
|
Dr. Ram krishnamurthy
Intel CRL
Date:
Monday, May 2nd, 2:00pm-3:00pm
Location:
750 CEPSR
|
Energy efficient circuit technologies for the sub-14nm era: challenges and opportunities
Abstract:
This lecture presents some of the prominent barriers to designing energy-efficient circuits in the sub-14nm CMOS technology regime and outlines new paradigm shifts necessary in next-generation multi-core microprocessors and systems-on-chip. Emerging trends and key challenges in sub-14nm design are outlined, including (i) device and on-chip interconnect technology projections, (ii) performance, leakage and voltage scalability, (iii) special-purpose hardware accelerators and reconfigurable co-processors for compute-intensive signal processing algorithms, (iv) fine-grain power management with integrated voltage regulators, and (v) resilient circuit design to enable robust variation-tolerant operation. Energy-efficient arithmetic and logic circuit techniques, static/dynamic supply scaling, on-die interconnect fabric circuits, ultra-low-voltage and near-threshold logic and memory circuit techniques, and multi-supply/multi-clock domain design for switching and leakage energy reduction are described. Special purpose hardware accelerators and data-path building blocks for enabling high GOPS/Watt on specialized DSP tasks such as encryption, graphics and media processing are presented. Power efficient optimization of microprocessors to span a wide operating range across high performance servers to ultra mobile SoCs, dynamic on-the fly configurability and adaptation, and circuit techniques for active/standby-mode leakage reduction with robust low-voltage operability are reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.
Biography:
Ram Krishnamurthy received the B.E. degree in electrical engineering from Regional Engineering College, Trichy, India, in 1993 and Ph.D. degree in electrical and computer engineering from Carnegie Mellon University in 1998. He has been with Intel Corporation since 1998, where he is Senior Principal Engineer and heads the high performance and low voltage circuits group at Circuits Research Labs, Intel Labs, Hillsboro, Oregon. He is responsible for research in high performance, energy efficient and low voltage circuits for microprocessors and SoCs. He holds 100 issued patents with over 50 patents pending and has published 150 conference/journal papers and 3 book chapters on high-performance energy-efficient microprocessor design. He serves as Intel¡¯s representative on the Semiconductor Research Corporation technical advisory board for circuits. He has served as associate editor of IEEE transactions on VLSI systems, guest editor of IEEE journal of solid-state circuits and on the technical program committees of ISSCC, CICC, and SOCC conferences. He served as Technical Program Chair/General Chair for the 2005/2006 IEEE International Systems-on-Chip Conference and presently serves on the conference¡¯s steering committee. He serves as ECE department adjunct faculty at Oregon State University, where he taught advanced VLSI design. He also serves on industrial advisory board of Oregon State University and State University of New York at Buffalo ECE departments. Krishnamurthy has received the IEEE International Solid State Circuits Conference Distinguished Technical Paper Award in 2012, IEEE European Solid State Circuits Conference Best Paper Award in 2012, Outstanding Industry Mentor Award from SRC in 2002, 2011 and 2015, Intel Awards for most patents filed in 2001 and most patents issued in 2003, Alumni recognition award from Carnegie Mellon University in 2009, and MIT Technology Review¡¯s TR35 Innovator Award in 2006. He has received the Intel Achievement Award, Intel Corporation¡¯s highest technical award, twice - in 2004 and 2008 for development and technology transfer of novel high-performance execution core arithmetic circuits and special-purpose hardware encryption accelerators. He is a Fellow of the IEEE and distinguished lecturer of IEEE solid-state circuits society.
|
|
Spring 2016 Seminars
|
|
Title:
Mostly Digital Phase-Locked Loops
Speaker:
Prof. Salvatore Levantino
Date:
Friday, Jan. 29th, 10am, 750 CEPSR
Title:
Memoryless Analog-to-Digital Conversion Using Delta-Sigma Modulators Without Reset
Speaker:
Prof. Nagendra Krishnapura
Date:
Thursday, Feb. 4th, 11am, 414 CEPSR
Title:
2-hr Short Course: Clock and Data Recovery Techniques for Optical Communication Systems
Speaker:
Prof. Kumar Lakshmikumar
Date:
Friday, Feb. 26th, 2pm, 750 CEPSR
Title:
Holistic Energy-Efficient Design in Optical Interconnects
Speaker:
Prof. Azita Emami
Date:
Monday, Feb. 29th, 3pm, 750 CEPSR
|
|
|
|
|
