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Fall 2015: Upcoming Seminars
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Prof. Rajit Manohar
Cornell University
Date:
Monday, Sept. 28th, 11:00am-12:00pm
Location:
414 CEPSR
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Engineering Neuromorphic Systems
Abstract:
The field of neuromorphic VLSI aims to replicate the amazing functionality of biological systems using conventional electronic circuits. Characteristics of biological systems are imitated with the goal of both understanding biology and replicating its efficiency for cognitive tasks. This talk provides an abbreviated history of the field, and presents some of the joint work we have been doing with IBM research on an all-digital approach to neuromorphic system engineering that culminated in TrueNorth--a low-power single chip million neuron system.
Biography:
Rajit Manohar is Professor of Electrical and Computer Engineering and a Stephen H. Weiss Presidential Fellow at Cornell Tech. He received his B.S. (1994), M.S. (1995), and Ph.D. (1998) from Caltech. He has been on the Cornell faculty since 1998 and the Cornell Tech faculty since 2012, where his group conducts research on self-timed systems. While at Cornell, he served as the Associate Dean for Research and Graduate studies in Engineering, the Associate Dean for Academic Affairs at Cornell Tech, and the Associate Dean for Research at Cornell Tech. He is the recipient of an NSF CAREER award, seven best paper awards, seven teaching awards, and was named to MIT technology review's top 35 young innovators under 35 for contributions to low power microprocessor design. He has designed a number of self-timed VLSI chips including the first high-performance asynchronous microprocessor, the first microprocessor for sensor networks, an event-based asynchronous chip-multiprocessor, a pipeline-configurable asynchronous FPGA, the first radiation hardened SRAM-based FPGA, and the first predictable large-scale neuromorphic architecture. He founded Achronix Semiconductor to commercialize high-performance asynchronous FPGAs.
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Prof. James Buckwalter
Univeristy of California, Santa Barbara
Date:
Friday, Oct. 2nd, 2:00pm-3:00pm
Location:
627 Mudd
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Fracking for 5G: Reconfigurable RF and High-Efficiency Millimeter-wave Circuit Techniques for Better Spectrum Usage
Abstract:
Mobile data demands are rapidly growing beyond the capabilities of licensed RF bands. To reach gigabit-per-second speeds, the cellular industry is considering a significant jump from RF to millimeter-wave bands over the next decade to alleviate congestion at RF bands. To take the most advantage of the current RF spectrum, software-defined radios are needed to hop to available spectrum. This talk will present our investigations into enabling CMOS circuits based on reconfigurable N-path filters for interference mitigation. At mm-wave bands, our ongoing work has demonstrated record output power from CMOS SOI millimeter-wave PAs and this talk will discuss system demands on transmit schemes, specifically outphasing, for high power and peak efficiency.
Biography:
James (Jim) Buckwalter received the Ph.D. degree in Electrical Engineering from the California Institute of Technology (Caltech), Pasadena, in 2006. He is currently a Professor of Electrical and Computer Engineering at the University of California, Santa Barbara (UCSB). He joined the faculty at the University of California, San Diego (UCSD), La Jolla, CA as an Assistant Professor in 2006 and was promoted to Associate Professor of Electrical and Computer Engineering in 2012. He is the recipient of an IBM Ph.D. Fellowship, Defense Advanced Research Projects Agency (DARPA) Young Faculty Award, NSF CAREER Award, and IEEE Microwave Theory and Techniques Society (MTT-S) Young Engineer Award.
More info. at UCSB RF & Mixed-signal Integrated System Lab
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Dr. Eric Nestler
Analog Devices
Date:
Friday, Oct. 9th, 2:00pm-3:00pm
Location:
627 Mudd
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Low Power Passive Switched Capacitor Analog Signal Processing Circuit and Systems
Abstract:
This talk will discuss several passive analog switched capacitor signal processing techniques. These types of signal processing would traditionally be done in the digital domain but in the analog domain the power requirements can be significantly reduced.
The switched capacitor techniques described here have been developed over the last few years and were part of the Lyric Semiconductor acquisition (now the Analog Garage) by ADI. These techniques have also been characterized in a released product.
The application of this Sampled Analog Technology (SAT) as passive embedded signal processing blocks enables lower power designs with increased signal processing capability.
In addition, the ADC requirements are also reduced, allowing a further reduction to the power consumption.
Several examples with measured and modelled results will be discussed.
Biography:
Eric Nestler is an ADI Division Fellow working in the Analog Garage, Cambridge, MA.
He received his BSEE from Tufts University and a MSEE from the University of Wisconsin, Madison.
After working at HP Medical and Symbolics, Inc he joined ADI in 1987.
Eric is the founder of the Energy Metering division in ADI that has shipped
over 500 Million energy metering parts during that last 20 years.
Eric left ADI in 2004 to work for two startups. The second, Lyric Semiconductor,
was acquired by ADI in June 2011.
While at Lyric Eric developed switched-capacitor analog signal processing
circuit technology that provides very low power for complex signal processing.
His present work is in Ultra Low Power Sampled Analog Technology (SAT) designs
applied to areas such as sensor interfaces, and ultrasound imaging.
Eric has over 25 patents issued in a number circuit and product areas.
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Prof. Seng-Pan U
University of Macau
Date:
Monday, Oct. 19th, 2:35pm-3:35pm
Location:
233 Mudd
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Energy Efficient SAR-Type ADC Design - Trends and Techniques
Abstract:
The evolving broadband wireless communication increasingly drives fast development on high-performance consumer portable smart and green gadgets with longer battery life, which leads to growing demands on high-speed ADCs with higher energy efficiency.
SAR-type ADCs which take advantages of CMOS technology downscaling for their "highly digital" implementation have been dominating large segments of high-speed and energy efficient ADCs with efficiencies down to fJ/conversion step at 100MHz+ sampling rate.
This talk provides firstly an overview of the state-of-the-art SAR-Type high energy-efficient ADCs, and then present the trends of the ADCs through the energy, speed and noise Analysis for various architectures including SAR & Binary-Search, Multi-bit SAR, Flash SAR and Pipeline SAR, Time-interleaved and etc.
Practical design examples and the state-of-the-art techniques will be also analyzed.
Biography:
Seng-Pan U (Ben) received joint Ph.D. degree from the University of Macau (UM) and the Instituto Superior Tecnico (IST), Portugal in 2002. He is currently Professor
and Deputy Director of State-Key Lab. of Analog & Mixed-Signal (AMS) VLSI of UM.
He is the co-founder of Chipidea Microelectronics (Macau), Ltd. (currently Synopsys
Macau Ltd) for AMS IP development and is also Senior Analog Design Manager and
Site General Manager. He published 130+ papers and 4 books in Springer and China
Science Press in the area of VHF SC filters, Analog Baseband for Multi-standard
wireless transceivers and Very High-Speed TI ADCs, and he co-holds 10+ US patents.
As the founding chair, he received the 2012 IEEE SSCS Outstanding Chapter Award. He received both the
2012, 2014 Macau Science & Technology (S&T) Invention and Progress Award. Both at the 1st time from
Macau, he received the S&T Innovation Award of Ho Leung Ho Lee Foundation in 2010, and also The
State S&T Progress Award in 2011. In recognition of his contribution in high-technology research &
industrial development in Macau, he was awarded by Macau SAR government the Honorary Title of Value
in 2010. He was also awarded as the "Scientific Chinese of the Year 2012". He is also advisor for 20+
student award recipients, incl. 2011 ISSCC Silk-Road Award & A-SSCC Student Design Contest, 2014
ESSCIRC Best Paper Award, 2015 SSCS Pre-doctoral Award. He is currently IEEE SSCS Distinguished
Lecturer (2014-2015), TPC of ISSCC, A-SSCC, AMS & RF Design Subcom Chair of VLSI-DAT and
Editorial Board member of Springer journal AICSP.
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Prof. Naehyuck Chang
KAIST
Date:
Wednesday, Oct. 21st, 2:00pm-3:00pm
Location:
627 Mudd
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Design Automation of Things, the Future of EDA
Abstract:
This talk introduces a new area of Design Automation, Design Automation of Things, that attempts to apply Electronics Design Automation design, optimization and synthesis methods to other applications (Things.) In this talk, we introduce the first step toward systematic electric vehicle (EV) design-time and runtime optimization. We develop instantaneous power consumption modeling of an EV by the curb weights, speed, acceleration, road slope, passenger and cargo weights, motor capacity, and so on, as a battery discharge model. To insure model fidelity, we fabricate a lightweight custom EV, perform extensive measurement, and derive model coefficients using multivariable regression analysis. We estimate the EV instantaneous power consumption of a given speed and route profiles and verify the estimation fidelity with a real test run data. This talk will introduce several research challenges and opportunities based on the EV model for accurate range estimation and minimum-energy EV design/operation.
Biography:
Naehyuck Chang is a Full Professor at the Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) from 2014. Before he joined KAIST, he was with the Department of Computer Science and Engineering, Seoul National University from 1997 to 2014. Dr. Chang also served as a Vice Dean of College of Engineering, Seoul National University from 2011 to 2013. His current research interests include low-power embedded systems and Design Automation of Things such as systematic design and optimization of energy storage systems and electric vehicles.
Dr. Chang is the Past Chair of ACM SIGDA (Special Interest Group on Design Automation), a Fellow of IEEE and an ACM Distinguished Scientist. Dr. Chang is the Editor-in-Chief of the ACM (Association for Computing Machinery) Transactions on Design Automation of Electronics Systems, and an Associate Editor of IEEE Transactions on Very Large Scale Integration Systems. He also served for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Embedded Systems Letters, ACM Transactions on Embedded Computing Systems, and so on, as an Associate Editor.
Dr. Chang is (was) the General Co-Chair of VLSI-SoC (Very Large Scale Integration) 2015, ICCD (International Conference on Computer Design) 2014 and 2015, ISLPED (International Symposium on Low-Power Electronics and Design) 2011, etc.
Dr. Chang is the Technical Program Chair of DAC (Design Automation Conference) 2016. He was the Technical Program (Co-)Chair of ASP-DAC (Asia and South Pacific Design Automation Conference) 2015, ICCD 2014, CODES+ISSS (Hardware Software Codesign and System Synthesis) 2012, ISLPED 2009, etc.
Dr. Chang is the winner of the 2014 ISLPED Best Paper Award, 2011 SAE Vincent Bendix Automotive Electronics Engineering Award, 2011 Sinyang Academic Award, 2009 IEEE SSCS International SoC Design Conference Seoul Chapter Award, and several ISLPED Low-Power Design Contest Awards in 2002, 2003, 2004, 2007, 2012, and 2014.
More info. at KAIST CAD4X Laboratory
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Prof. Ramesh Karri
New York University
Date:
Friday, Nov. 6th, 2:00pm-3:00pm
Location:
627 Mudd
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Trustworthy Hardware
Abstract:
Hardware security and trust is an important design objective similar to power, performance, reliability and testability. I will highlight why hardware security and trust are important objectives from the economics, security, and safety perspectives. Important learning outcomes of this talk include (i) understanding simple gotchas when traditional DFT, test, and validation techniques are used (scan chains, JTAG, SoC test, assertion based validation), (ii) understand how traditional DFT, test and validation techniques can be used to improve hardware security and trust and finally (iii) understand "Design for Trust" approaches that can provide testability without compromising security and trust.
Biography:
Ramesh Karri (http://eeweb.poly.edu/karri/) is a Professor of Electrical and Computer Engineering at Polytechnic Institute of New York University. He has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego. His research interests include trustworthy ICs and processors; High assurance nanoscale IC architectures and systems; VLSI Design and Test; Interaction between security and reliability.
He has over 150 journal and conference publications in these areas. He has written two invited articles in IEEE Computer on Trustworthy Hardware, an invited article on Digital Logic Design using Memristors in Proceedings of IEEE and an Invited article in IEEE Computer on Reliable Nanoscale Systems.
He was the recipient of the Humboldt Fellowship and the National Science Foundation CAREER Award. He served on the 2006 DARPA ISAT study on Trust in Integrated Circuits. He is the area director for cyber security of the NY State Center for Advanced Telecommunications Technologies at NYU-Poly; Hardware security lead of the Center for research in interdisciplinary studies in security and privacy -CRISSP (http://crissp.poly.edu/), co-founder of the Trust-Hub (http://trust-hub.org/) and organizes the annual red team blue team event at NYU, the Embedded Systems Challenge (http://www.poly.edu/csaw2012/csaw-embedded).
He cofounded and served as the chair of the IEEE Computer Society Technical Committee on Nanoscale architectures. He is a cofounder and steering committee member of the IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH). He is the Program Chair (2012) and General Chair (2013) of IEEE Symposium on Hardware Oriented Security and Trust (HOST). He is the Program Co-Chair (2012) and General Co-Chair (2013) of IEEE Symposium on Defect and Fault Tolerant Nano VLSI Systems. He is the General Chair of the 2013 NANOARCH. He serves on several program committees. He is the Associate Editor of IEEE Transactions on Information
He has organized invited tutorials on various aspects of Trustworthy Hardware (including at 2012 VLSI Test Symposium, 2012 International Conference on Computer Design, 2013 IEEE North Atlantic Test Workshop, 2013 Design Automation and Test in Europe). He currently advises eight PhD students and mentors two postdoctoral candidates. His research is funded by NSF (IGERT, Scholarship for Service, Capacity Building, CRI, Cybersecurity), DOE (GAANN), AFRL, ARO, Cisco and Intel. He organizes the annual Embedded Systems Challenge to promote a challenges-based approach to hardware trust validation and embedded systems education.
More info. at http://eeweb.poly.edu/karri/
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Prof. Dimitri Galayko
University Paris VI (UPMC-Sorbonne)
Date:
Friday, Dec. 11st, 2:00pm-3:00pm
Location:
627 Mudd
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Advanced conditioning circuits for capacitive transducers in vibration energy harvesters
Abstract:
Miniature energy harvesting devices are believed to be a key for the autonomy of smart sensors. Kinetic energy, e.g., vibrations, is present in many environments, and generation of electricity out of mechanical vibrations is an active research area in many groups. One of the promising technique for electromechanical conversion is offered by capacitive transducers, where the electricity is generated when a charged variable capacitor decreases its capacitance because of motion of one of its electrodes. This harvesting technique is well-suitable for miniaturisation, since the sensors are often implemented in MEMS silicon technologies.
In order to maximise the generation of electricity, the variable capacitor needs a dynamic electrical bias. This is achieved by the conditioning electronics, which controls the energy conversion process by defining the charge-voltage cycle on the variable capacitance. Since the power converted by electrostatic devices is not above few tens of microwatts, very stringent requirements are applied to the conditioning electronics.
The seminar presents the results of recent studies on family of conditioning circuits for electrostatic transducers which implement rectangular QV cycle. These circuits are based on the charge pump architecture, and have a common property of self-synchronisation with the external vibrations, so simplifying the design of the control electronics. Some of these circuits offers a very precious feature: accumulation of the converted energy inside of the conditioning circuit. This allows an easy control of the biasing of the transducer, and opens a possibility for adaptive operation of the energy harvesting system. Some specific issues such as electromechanical coupling and interface with the load will also be discussed.
Biography:
Dimitri Galayko graduated from Odessa State Polytechnich University (Ukraine) in 1998, he received his master degree from Institut of Applied Sciences of Lyon (INSA-LYON, France) in 1999. He made his PhD thesis in the Institute of Microelectronics and Nanotechnologies (IEMN, Lille, France) and received the PhD degree from the University Lille-I in 2002. The topic of his PhD dissertation was the design of microelectromechanical silicon filters and resonators for radiocommunications. Since 2005 he is an associate professor in University Paris VI (UPMC-Sorbonne) in the LIP6 laboratory. His research interests include study, modeling and design of nonlinear integrated circuits for sensor interface and for mixed-signal applications. He is a member of TC Nonlinear Circuits and Systems of IEEE CAS society, he served as track chair, RCM and reviewer in several CAS conferences and journals. He has been leader of two French national collaborative grants (HODISS, HERODOTOS), and of grant ULYSSE of Campus France (2012), organizer and chair of several invited sessions at conferences ISCAS et ICECS. He is co-author of 18 journal papers, more than 70 conference communications and 4 patents.
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Fall 2015 Seminars
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Title:
Engineering Neuromorphic Systems
Speaker:
Prof. Rajit Manohar
Date:
Monday, Sept. 28th, 11:00am-12:00pm, 414 CEPSR
Title:
Fracking for 5G: Reconfigurable RF and High-Efficiency Millimeter-wave Circuit Techniques for Better Spectrum Usage
Speaker:
Prof. James Buckwalter
Date:
Friday, Oct. 2nd, 2:00pm-3:00pm, 627 Mudd
Title:
Low Power Passive Switched Capacitor Analog Signal Processing Circuit and Systems
Speaker:
Dr. Eric Nestler
Date:
Friday, Oct. 9th, 2:00pm-3:00pm, 627 Mudd
Title:
Energy Efficient SAR-Type ADC Design - Trends and Techniques
Speaker:
Prof. Seng-Pan U
Date:
Monday, Oct. 19th, 2:35pm-3:35pm, 233 Mudd
Title:
Design Automation of Things, the Future of EDA
Speaker:
Prof. Naehyuck Chang
Date:
Wednesday, Oct. 21st, 2:00pm-3:00pm, 627 Mudd
Title:
Trustworthy Hardware
Speaker:
Prof. Ramesh Karri
Date:
Friday, Nov. 6th, 2:00-3:00pm, 627 Mudd
Title:
Advanced conditioning circuits for capacitive transducers in vibration energy harvesters
Speaker:
Prof. Dimitri Galayko
Date:
Friday, Dec. 11st, 2:00-3:00pm, 627 Mudd
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