Abstract:

As a consequence of a variety of constraints, many subjects in science and engineering education do not include a laboratory experience. Yet, hands-on laboratory exercises can substantially enhance education effectiveness. At MIT, we are harnessing Internet technology to enable students to remotely access real laboratories and carry out experiments from anywhere at any time. This talk will describe and demonstrate the MIT Microelectronics WebLab, an online microelectronics device characterization laboratory. It will also discuss educational experiments carried out using WebLab from MIT, Singapore, and Sweden.

Abstract:

In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important aspect of high-performance digital integrated circuit design, and indispensable for first-time-right hardware and cutting-edge performance. The presentation will discuss the methodology, analysis, synthesis and modeling aspects of this problem. These aspects of the problem will be compared and contrasted in the ASIC and custom (microprocessor) domains. Particular attention will be paid to statistical timing analysis; desirable attributes that would render such an analysis capability practical and accurate will be enumerated. The algorithms and activities being pursued in IBM to solve the statistical timing problem will be briefly discussed.

Abstract:

With the emerging market for the wireless LAN standards 802.11a and g, the need exists to provide radio solutions that integrate these standards together with the popular "b"-standard into a single receiver. These so called "combo"-solutions pose stringent requirements on the radio's VCO in terms of phase noise and tuning range. Preferably a single VCO, in combination with selectable frequency division, provides the capability of covering all RF bands (respectively 2.412-2.484GHz and 5.18-5.805GHz for the b,g and a standard).

This talk will highlight some recent developments in the design of LC tuned VCOs. The first part of the talk will deal with the role that the varactor plays in the tuning linearity and noise upconversion of LC-tuned VCOs. The topics addressed will include: tuning dependency on bias current, linearization of the tuning curve when using varactors with an abrupt C(V) characteristic, bias noise upconversion by the varactor through AM-and CMM-to-PM conversion, and differential tuning as a way to reduce noise upconversion.

The second part of the talk will deal with quadrature oscillators. It will be shown how quadrature oscillators can be used with advantage in potential 802.11 architectures. After a brief overview of existing quadrature VCO topologies, an alternative concept of quadrature coupling of LC oscillators is introduced. It uses injection-locking through common mode inductive coupling to enforce quadrature. The technique provides quadrature over a wide tuning range without introducing any phase noise or power consumption increase.

Abstract:

At the present time, analog and RF CMOS design suffer from a variety of self-imposed constraints which severely limit both the efficiency of the design process and the capabilities of product ICs. These constraints are not real, but are instead self-inflicted due to the continued use of a design infrastructure which has been overstretched and which has outlived its usefulness. At its roots, the problem is one of an overly deconstructed and segmented approach to the MOS transistor in understanding, modeling, usage, and design implementation.

This presentation will outline a fundamental rebuilding and re-generalization of the entire approach to describing the MOS transistor and the methods by which the ubiquitous MOSFET is used in circuit design. Rather than being split up into separate pieces, this new approach involves the construction of an overarching structure through which process technology, modeling, design usage, and design optimization all become part of one coherent whole. It will be shown that not only can the MOS transistor be interpreted in a much simpler and more comprehensible fashion, but that this interpretation is universal across processes and technologies. Some examples, taken from real situations where ICs have been designed and sold in large quantities, will be described, clearly demonstrating how many of the self-imposed constraints of older methods can be broken, allowing for fuller use of the capabilities of modern deep-submicron CMOS technology. Finally it will be noted that by this generalization of the behavior of the MOS transistor, the methods thus developed can be generalized beyond CMOS to future nanotechnology devices.

Abstract:

The continued scaling of CMOS transistors provides significant challenges and opportunities for designers of mixed signal systems. We will review scaling trends and discuss its implications for incipient mixed signal systems. Using examples drawn from high- speed digital, low frequency as well as Radio frequency analog design applications, we will describe the impact of reducing voltages while simultaneously increasing leakage currents. We will also discuss, the space of realizable systems in the context of available device bandwidth and integration levels.

Abstract:

We design in the era of the ever shinking power supply. Many of the basic tried-and-true cells that are in our textbooks are or will soon be rendered unuseable due to this unrelenting downward march of Vdd. In the face of such challenges, some have suggested that floating-gate MOS (FGMOS) transistors are useful devices for designing low-voltage circuits, mainly because they offer us the possibility of lowering their threshold voltages by programming their floating-gate charges appropriately. However, since Shibata's introduction of the neuron MOS concept, we have realized that FGMOS transistors have more to offer than programmable threshold voltages. We can capacitively couple as many control gates as we would like into the floating gate of a FGMOS transistor, which opens up to us many new circuit topologies, many of which are very quite attractive for operation on a low power supply voltage. In this talk, I will discuss some of our recent efforts in charting this new design space.

Abstract:

This talk examines the fundamental reasons for the large power dissipation of dynamical analog circuits with large dynamic range. It is shown that by allowing the internal attributes of circuits to vary in an appropriate manner, such fundamental limitations can be bypassed in certain cases. The talk reviews several techniques, developed by the analog group of CISL in the past several years, which make possible internally varying analog circuits with invariant external behavior. These techniques include companding, dynamic biasing, and dynamic impedance scaling. Experimental results from recently developed chips, which demonstrate over an order of magnitude improvement compared to the state of the art, are described.

Abstract:

Advanced silicon technologies have opened the doors to implement very high-speed links for electrical, optical and wireless connections. In parallel to higher bandwidth requirements, there is also a pressing need for higher levels of integration in the wired and wireless communication fields to bring the cost and power dissipation down while still complying with stringent link requirements such as sensitivity, jitter and bit-error-rate.

In this talk, we will review the research activities undertaken by the Communication Circuits and Systems department at IBM T.J. Watson Research Center, Yorktown Heights, NY in the area of multi-Gb/s and microwave links using CMOS and SiGe technologies.

Abstract:

Power has emerged recently as a primary design variable in high-end microprocessors. Naive focus on performance leads the system design into inefficient power-performance operation. In order to design more effectively it is important to have power-performance measures to guide the design from technology through circuit design to micrarchitecture. The first part of the presentation highlights hardware intensity, a measure of the power-performance efficiency of a circuit design. Relations are derived using this measure which have practical consequences for power budgeting and for joint circuit-microarchitecture tradeoffs. The second part of the presentation focusses on adding power to the analysis of microarchitectural pipelining. The results illustrate the hazards of ignoring power, and the major impact it can have on optimal pipelining. The talk concludes with speculations on further research opportunities in this area.

Abstract:

Backplanes contain a lot of interconnect to connect several system parts. The required data bandwidth of interfaces within/between systems continues to grow and therefore there is always a drive to increase backplane communication speed. Sometimes the question is posed whether this type of communication will be replaced by optical links soon.

This presentation shows that electrical is certainly not at its end of life. Proper signalling, transmission lines and characteristic design can boost the performance to 10Gb/s/channel (and probably beyond). Furthermore electrical has certainly a strong advance: low-cost. The presentation discusses several bus and signalling concepts, shows problems and limitations, but also solutions and opportunities for the future enabled by technology improvements. Optical links seem not really competitive yet for this kind of application. This brings up the conclusion that (new) electrical links remain the preferred solution for the foreseeable future.

Abstract:

Integrated circuit front ends are used extensively in both research and commercial applications of radiation detectors. Examples range from particle physics, where modern detectors involve tens of millions of sensors accumulating data at rates of terabytes per second, to handheld nuclear medicine probes used to guide surgery. Key circuit design goals are: power-constrained front-end noise optimization, high precision voltage and time measurements in a mixed-signal VLSI environment, radiation tolerance, and high-density interconnect to the sensors. This talk will describe some CMOS circuit techniques developed to achieve these goals. The expected impact of CMOS scaling on future analog performance will also be discussed.

Slides of the talk

Abstract:

The growth of the semiconductor IC industry over the past few decades has been fueled by continued scaling of transistors to enable higher packing density, faster circuit speed, and lower power dissipation. New materials and device structures are needed to continue the CMOS performance trend. In this talk, I will discuss some of the technology options for nano-scale CMOS technology. These options include ultra-thin channel single- and double-gate MOSFETs and alternative materials for the channels and gate stacks.

Abstract:

This talk will give an overview of well-known signal processing techniques used in lower speed wireline and wireless applications, applied to high-speed optical communications. After an introduction on today's optical network architecture and optical channel impairments, we review modulation techniques for optical communications, fiber equalization, forward error correction, with special emphasis on VLSI implementation.

Abstract:

Optical transmission systems based on 40 Gb/s E-TDM are nearing their commercial introduction. The push for higher payload date rate has spurred interest in optical systems with single-channel capacity beyond 40 Gb/s. Reaching such high data rates will require further improvements not only in electronics, but also in packaging, O/E-E/O conversion and measurements. In our talk, we will focus on the electronics and give an overview of the strengths of different semiconductor technologies needed to build transmitters and receivers at 40 Gb/s and beyond. We will give a number of analog and digital circuit examples, mainly based on InP and SiGe HBT's.

Abstract:

Wireless LANs based on the IEEE 802.11 standard have achieved wide customer acceptance in the enterprise environment. They are expected to continue to expand in popularity and become ubiquitous communication systems even in private and public places. This paper discusses the basics of the wireless LAN physical layer, focusing on radio tranceiver specifications and design options.

Abstract:

Broadband wireless communication systems require high-speed, high-resolution Analog-to-Digital (A/D) Converters designed in digital CMOS process. One such application in cellular base stations requires the A/D Converter to digitize multiple channels at IF frequencies as high as 70 MHz with resolutions greater than 13 bits. Multi-bit Pipelined architecture for Analog-to-Digital conversion have been shown to provide high throughput at low power consumption. However practical realizations of these converters in digital CMOS process suffer from component mismatches, lower amplifier gains, offsets and charge injection errors, limiting their linearity to 8-10 bits of resolution at sampling rates in only tens of MHz. Existing Calibration Techniques to improve the resolution of the A/D Converters suffer from several drawbacks.

This talk will focus on background calibration techniques to improve the resolution of Pipelined Analog-to-Digital Converters in digital CMOS process. A general idea of the proposed technique is to adaptively correct for systematic errors in pipelined A/D converter using a least mean squares approach. The technique will be shown to achieve high linearity with minimal real estate and power consumption.

Abstract:

The increasing demand for affordable and portable wireless communication systems has motivated substantial research into the realization of monolithic transceivers. The use of low-cost CMOS technology is of particular interest since it provides the possibility of integrating analog and digital circuitry on the same chip. Furthermore, the trend toward shifting more complexity from the analog to the digital domain in favor of robust and flexible performance, suggests more functionality should be implemented in the digital domain. Of particular interest is channel selection filtering, an essential function of any receiver. Also, the recent surge in high-data-rate wireless applications (e.g. wireless local area networks, multimedia) advocates the use of spectrally-efficient modulation schemes.

In this talk, we start with a review of the classical and modern receiver architectures suitable for a single-chip realization. Also, low-voltage realizations of RF building blocks (low-noise amplifier and mixer) will be discussed. Then, two research projects at the University of Toronto on a low-cost CMOS wireless video communication system are highlighted. First, Hierarchical QAM, a new DC-free spectrally-efficient modulation scheme is presented. Second, the realization of a delta-sigma decimation filter which also performs as a channel selection and approximate root-Nyquist pulse-shaping filter is described.

Abstract:

Challenges for ultra large-scale silicon products are summarized under five major headings: power-delivery, optimization, asychronization, re-use, and design-skills. Each is described with a broad brush and with illustrating examples from the viewpoint of the chip and circuit designer of microprocessor products. Synthesis systems are important tools for meeting these challenges. Briefly descriped is an advanced synthesis system for domino with 2Ghz silicon validation results. This is a workshop-style seminar with no distributed materials or recordings.

Abstract:

Boolean Satisfiability is probably the most studied of combinatorial optimization/search problems. Significant effort has been devoted to trying to provide practical solutions to this problem for problem instances encountered in a range of applications in Electronic Design Automation (EDA), as well as in Artificial Intelligence (AI). This study has culminated in the development of several SAT packages, both proprietary and in the public domain (e.g. GRASP, SATO) which find significant use in both research and industry. Most existing complete solvers are variants of the Davis-Putnam (DP) search algorithm. In this talk I will describe the development of a new complete solver, Chaff, which achieves significant performance gains through careful engineering of all aspects of the search - especially a particularly efficient implementation of Boolean constraint propagation (BCP) and a novel low overhead decision strategy. Chaff has been able to obtain one to two orders of magnitude performance improvement on difficult SAT benchmarks in comparison with other solvers (DP or otherwise), including GRASP and SATO. This is joint work with Matt Moskewicz, Conor Madigan, Ying Zhao and Lintao Zhang.

Abstract:

As CMOS technology scales to deep submicron lengths, designers face new challenges in determining the proper balance of aggressive high performance devices and lower performance devices to optimize system power and performance for a given application. Determining this balance is crucial for battery powered handheld devices where device leakage and active power limit the available system performance. This talk will explore this question and describe research in developing low power communication systems which exploit the capabilities of advanced CMOS technology.

Abstract:

Since power consumption is now a first-class design contraint, "power-awareness" is a necessary aspect of modeling and design. This is true for all stages of design and at all levels of abstraction. In this talk, we will focus on power-aware design at the microarchitecture definition stage. We start by presenting our group's work on early-stage, workload-driven power-performance modeling. Augmenting the current architectural simulation tools to include energy behavior of the unit-level components is the first step in conducting research in this emerging new area. We also describe the model validation methods that we are pursuing to understand the relative and absolute accuracy implications of such early-stage models. In the second part of the talk, we describe some of the specific power-aware microarchitecture ideas that we have studied. We present simulation-based and analytical results to understand: (a) the power-performance efficiency benefits of dynamic adaptation and throttling of on-chip computing resources: e.g. issue queues and instruction fetch bandwidth; (b) the fundamental limits of scaling within a given microarchitectural paradigm: e.g. super scalar, with and without simultaneous multithreading (SMT) as well as chip multiprocessing. We also address the microarchitectural support issues for coarse- and fine-grain clock gating as well as Vdd (power) gating; and, we project the effect of such "gating" methods on power-performance scalability.

Abstract:

Designing CMOS devices for high-performance servers has always been a challenge. Scaling devices to keep up with the higher performance Moore's Law demands from each generation has already forced gate lengths below 0.1um and gate oxides below 1.5nm, so ever more creative methods of technology improvement -- beyond simple scaling -- are needed. To face this challenge, IBM has been a leader in introducing many new materials, such as Cu wires and SiLK(TM) low-K intermetal dielectric, and new technologies, such as SOI and strained-Si. This talk will cover many of these technologies, and how they affect the device designers task, particularly focusing on SOI CMOS design. In addition, the rise of the internet, high-speed networking, and mobile computing have introduced a new set of requirements for semiconductor technologies. Various extensions of SOI CMOS that attempt to meet these needs, such as adding devices optimized for RF or low-power performance, as well as embedding DRAM into SOI logic processes, will also be touched on briefly.

Abstract:

This presentation reviews recent advances in SOI circuit design for high-performance digital applications with particular emphasis on the circuit / design issues resulting from the unique SOI device structure. The technology / device choices / requirements and design challenges are highlighted. Unique design aspects for partially-depleted SOI , such as parasitic bipolar effect, hysteretic Vt variation, temperature dependence, and scaling implications, are addressed. Circuit techniques to improve the noise immunity and performance, and design methodology to handle and contain the hysteretic Vt variation are discussed.

Abstract:

The mission of the VLSI Design and Architecture department at IBM Research is to contribute VLSI design, microarchitecture, and performance expertise into leading edge microprocessor designs and to explore new microarchitectures, system designs and organizations, code optimization, circuits, and design tools and methodologies. I will give a brief overview of ongoing projects in our department and illustrate how we are able to drive innovative ideas from Research into real products. I will then spend most of the time summarizing IBM Research's Global Technology Outlook.

Abstract:

A movement away from specialized bipolar process technology to pure digital CMOS technology has characterized the last fifteen years of analog IC design. Merged BiCMOS technology has not become a mainstream option as a result of the high incremental process costs for the BiCMOS devices. Challenging the analog designer is the fact that maximum operating voltages have fallen concurrently with each smaller geometry generation of core CMOS transistors. Designers have moved from a 10V environment to a 3.3V environment with surprisingly little trouble. The start of the new century brings new challenges as the maximum operating voltage of 0.15u to 0.1u process technology has dramatically reduced to 1.5V - 1.0V. At the same time, modular BiCMOS is evolving. The costs of these technologies, as a percentage of the total wafer cost, have declined significantly. Modular SiGe bipolar devices now challenge the performance space once occupied only by GaAs. Copper interconnect systems, low k dielectrics and modular substrate engineering offer, for the first time, high Q passive inductors on chip.

In this talk, we will examine the current process technology options available to the analog designer and use our foggy crystal ball to predict whether core digital CMOS or modular BiCMOS will emerge as the mainstream choice for mixed-signal and RF chip designs in the early part of this.

Abstract:

This talk will start with a brief overview of the challenges in embedded SoC design. We will then describe some work with Jason Fritts to evaluate programmable architectures for single-chip video processors. We performed a large number of experiments using the MediaBench benchmarks to evaluate VLIW and superscalar processors' performance on media processing. These experiments helped us determine the effectiveness of a number of architectural features for media processing.

Abstract:

A MOSFET-C channel selection filter for a direct conversion WCDMA receiver is presented. This 5th order elliptic filter achieves 1.8 dBV in-band IIP3, +27.8 dBV out-of-band IIP3, +93.8 dBV out-of-band IIP2, 46.7 uV rms input-referred noise, and dissipates 6.2 mW from a 2.7 V supply; the on-chip continuous automatic tuning system dissipates 4.1 mW.

Abstract:

In the decade before World War II, Black, Bode, and Nyquist put the concept of feedback on a firm theoretical base that made highly reliable, practical applications possible. The impact of feedback is far broader than how it transformed electrical engineering, both in what could be accomplished and in how EEs are educated. Feedback is ubiquitous. It has influenced virtually every area of intellectual endeavor; it is integral to the physical realization of nearly everything that comprises today's information society. This talk begins to address several questions concerning feedback. Among them are:

1. What were the earliest uses of feedback and why didn't these lead to a more general usage?
2. What was the reaction to Black's amplifier proposal?
3. What are some of the implications of the concept of feedback?

Abstract:

The field of radio frequency integrated circuit (RFIC) design is currently enjoying a renaissance, driven by the explosive growth in wireless applications.Because of this sudden and unexpected growth, there has been a frenzied scramble to train RF engineers to meet the high demand. A major challenge in this task is that RF design is multidisciplinary in nature, requiring knowledge of communications and signal propagation theory, transceiver architectures, and circuit design. To address the education and research issues associated with the demand,this talk will present an intensive first-year graduate course designed specifically to produce competent RFIC designers in one year along with onging research conducted in the Cornell Broadband Communications Research Lab (CBCRL).

Abstract:

This work presents a novel technique for the design of continuous time analog filters with high dynamic range and low power dissipation. The essence of the method is to break up the required dynamic range of the filter in smaller ranges, and utilize separate filters in each one of them. This is done in such a way that the output is not disturbed whenever a different filter takes over. Very serious power dissipation and chip area savings will be shown to result from this technique.

Abstract:

Over the last twenty years numerous studies dealing with Gm-(grounded)C biquad filter design have been published. While each of these fine publications provides a "good set" of filter topologies none of them seems to clearly identify the "complete set".

In this talk I will derive the "complete set" of practical HP and notch biquad topologies. The result of this derivation is quite unexpected: there are only five distinct topologies (two notches and three HP). Two of them require precise Gm matching while the other three do not.

Abstract:

A quadrature "splitter" assumes a reference clock at frequency f_in, f_min <= f_in <= f_max. The output is two equal-amplitude signals c(t) and s(t) both periodic with frequency f_in but spaced exactly one-quarter of a period apart: i.e., c(t) = s(t+T/4), T=1/f_in. Such a quadrature pair can be used, for example, to generate single sideband modulation. The suppression of the undesired sideband depends directly on the accuracy of the quadrature signals. We describe such a scheme, which injection-locks a cascade of ring oscillators in such a manner as to generate extremely accurate quadrature for f_in in excess of 2GHz with a tuning range of at least 100MHz. Our scheme places no requirements on the waveform of the reference clock. Simulation and preliminary experimental data confirm our claims of quadrature accuracy on the order of 0.1 degrees of phase. When used for a SSB modulator, this implies suppression of the undesired sideband by at least 50dB.

Injection-locking is related to but distinct from phase locking. In particular, there is no requirement for a low-pass "loop" filter, hence no issue of loop stability. A brief discussion of the theory of injection-locking will be presented.

Abstract:

Logic verification continues to be considered one of CAD`s most difficult problems, highlighted with the discovery of the Pentium bug dilemma. This talk reviews certain current innovations addressing such problems. A new method will be discussed, based on what has become known as Recursive Learning Technique. This proposed technique has its cornerstone in Boolean implication techniques -- proven most powerful when traditional approaches such as OBDD fail. In fact, Recursive Learning was the first to verify the ISCAS benchmark circuits -- discovering some bugs in the process. This work has won the l996 IEEE Transactions on CAD/Best Paper Award, patented that same year. Several CAD companies currently implement this technique in their tool.

Abstract:

The problem of the evaluation of phase noise in integrated LC-oscillators is discussed. We show that is possible to obtain a simple expression for the output phase noise that takes into account the circuit non-linearities, avoiding the use of "black box" simulators. Using simple physical arguments, supported by experimental data, we show that some upconversion mechanism usually neglected, as those arising from indirect stability or from AM/PM conversion, may be instead dominant and invalidate the noise vs. power trade-off. These considerations will be applied to the design of two circuits: a 2.5 GHz bipolar oscillator with an Automatic Amplitude Control loop, and a 5 GHz CMOS oscillator for Bluetooth standard.