Partially-depleted silicon-on-insulator (PD-SOI) has emerged as a leading technology for high-performance, low-power deep-submicron digital integrated circuits. PD-SOI technology offers reduced parasitic capacitance associated with source and drain diffusion regions and reduced reverse-body effect in FET series connections. These effects allow for higher speed (or lower power) operation in PD-SOI than in bulk CMOS. In addition, PD-SOI eases the tradeoff of logic functionality vs speed for a given channel-connected component (CCC), allowing for larger CCC's. The main drawback to this technology is that the body of a PD-SOI transistor is floating. This leads to uncertainties in body potential and hence, the threshold voltage. For many circuits, the design margining required to protect against this uncertainty can erode the potential performance advantages. In addition, a floating body can lead to a parasitic bipolar effect which can result in noise failures. To deal with these issues, existing static timing and static noise tools must be enhanced to understand the unique features of PD-SOI technology.
Our work in this area has lead to a model that captures the dominant physical mechanisms affecting floating body potential, and a CAD tool which implements this model while leveraging switching and circuit topology information to provide accurate bounds on the floating body potential. Model parameters for our CAD program are extracted once, during a pre-characterization step of a given PD-SOI technology, based on transistor level simulations. The actual body voltage estimation requires no transistor level simulation. This CAD tool can be easily incorporated into existing static timing and static noise analyzers to make them "SOI aware." A more active approach to bounding floating-body potential in practice might be to keep PD-SOI circuits stimulated with known input vectors, during periods of inactivity. Hence, hysteresis can be used to hold controlled body voltage variations. The feasibility of this approach, and the exact nature and frequency of the input vectors remain to be investigated.
We describe a techniques to estimating the floating body potentials of partially-depleted silicon-on-insulator (PD-SOI) circuits under steady switching activity and under initial activity after a long period of quiescence. The approach is based on a unique atate digram abstraction of the PD-SOI FET that captures all of the essential device physics. This pciture yields a simpel analytic model of the body voltage which is used within the context of a prototype transistor-level static timign analysis engine. Results are presented that demonstrate the accuracy of the analytic body-voltage model and the reduction in delay uncertainty possible with this technique.
Partially depleted silicon-on-insulator (PD-SOI) has emerged as a technology of choice for high-performance, low-power deep-submicrometer digital integrated circuits. An important challenge to the successful use of this technology involves successfully managing and predicting the large "uncertainties" in the body potential and consequently the threshold voltages that can result from unkown past switching activity. In this paper, we present a unique state-diagram abstraction of the PD-SOI field-effect transistor that can capture all of the past switching activity determining the body voltage. Based on this picture, four differen estimation schemes are discussed that increasingly bound floating body uncertainty based on more detailed knowledge of switching activity. Using these estimation techniques with a prototype transistor-level static timing analysis engine, we demonstrate both the accuracy of the estimation and the reduction in delay uncertainty possible with these techniques.
This paper reviews recent progress in making circuit-level CAD tools for the design of digital integrated circuits SOI-aware, specifically transistor-level static timing and static noise analysis tools. This involves abstracting the SOI device physics of the floating body, allowing estimates of the body voltage variation under various switching activity assumptions. These body voltage estimates are then applied as "initial conditions" in the constitutent simulations of the static analysis. Results are presented for a prototype static timing analysis tool and a commerical static noise analysis tool.
In this paper, we extend transistor-lvel static noise analysis tools to consider the unique features of partially-depleted silicon-on-insulator (PD-SOI) technology: floating-body-induced threshold voltage variations and parasitic bipolar leakage currents. This involves a unique state-diagram abstraction of the device physics determining the body-potential of PD-SOI FETs. Based on this picture, a simple model of the body voltage is derived which takes into account modest knowledge of which nets have dependable, regular switching activity. Results are presented using a commercial static noise analysis tools incorporating these extensions.