Handouts :
| #1 | Syllabus | |
| #2 | Problem Set #1 | |
| #3 | Problem Set #2 | |
| #4 | Problem Set #1 Solutions | Hardcopies available |
| #5 | Problem Set #3 | |
| #6 | Problem Set #2 Solutions | Hardcopies available |
| #7 | Problem Set #4 | |
| #8 | Problem Set #3 Solutions | Hardcopies available |
| #9 | Problem Set #5 | |
| #10 | Problem Set #4 Solutions | Hardcopies available |
| #11 | Problem Set #6 | Hardcopies available |
| #12 | Problem Set #5 Solutions | Hardcopies available |
| #13 | Sample Midterm | Hardcopies available |
| #14 | Problem Set #7 | |
| #15 | Problem Set #6 Solutions | Hardcopies available |
| #16 | Problem Set #8 | |
| #17 | Problem Set #7 Solutions | Hardcopies available |
| #18 | Problem Set #9 | |
| #19 | Problem Set #10 & Mini Project | |
| #20 | Problem Set #8 Solutions | Hardcopies available |
| #21 | Problem Set #9 Solutions | Hardcopies available |
| #22 | Problem Set #10 Solutions | Hardcopies available |
Lecture Information & Reading Assignments :
| Lecture #1 (09/05) | Introduction to VLSI
History, Technologies, Challenges, Introduction to MOS IC devices, Examples of simple layouts |
| Lecture #2 (09/10) | Reading Text : p 39-41, 190-193, 202-203, 210-212
Intro to MOS logic circuits Switch notation, MOS switches, Rough electrical model, symbols, non-idealities, Charging/discharging through NMOS/PMOS, Multi-input switches, properties, Swing |
| Lecture #3 (09/12) | Reading Text : Chap 2 thru P-50 (skim static diode current)
MOS logic circuits , Stick diagrams, NAND/NOR implementation in CMOS, Ratioed Logic, Pseudo NMOS logic, Intro to Pass Logic |
| Lecture #4 (09/17) | MOS logic circuits continued, Intro to Static
restoring logic, Pass logic, Example of 4-transistor XOR, Dynamic latch, Precharged or Dynamic logic PART 2 of course started, Intro to semiconductors, doping. |
| Lecture #5 (09/19) | Semiconductor Properties, Impurities,Detailed analysis of pn junction diodes, MOS capacitors. |
| Lecture #6 (09/24) | Reading Text : p50-p62.
Derivation and detailed analysis of Threshold voltage of MOSFETs . |
| Lecture #7 (09/26) | Readint Text : p439-446, p464-470
First order Transistor model continued. Current and capacitance derivations, Second order effects started...short channel, narrow channel and vertical variations. |
| Lecture #8 (10/01) | Reading Text : p82-89, p97-104
Second order effects continued...discussed mobility variation, subthreshold conduction, Leakage currents. Interconnects : resistance, electromigration, capacitance. |
| Lecture #9 (10/03) | Interconnects continued...Detailed analysis of an example layout and calculation of various capacitances and resistances. |
| Lecture #10 (10/08) | Interconnects contd...discussion on wire inductances, heat removal.
Part 3 of course started on fabrication and layout rules. Crystal growth, pattern definition, Material removal/addition. |
| Lecture #11 (10/10) | Reading Text : p108-128
Fabrication steps for CMOS, Latchup, discussion on design rules. |
| Lecture #12 (10/15) | FAbrication and Layout continued..., discussed Mask alignment, Line width variation, Design Rule complexity, Few design rule examples , trade-offs, Artifact Rules, etc. |
| Lecture #13 (10/17) | discussion of yield under Fabrication and Layout.
Part 4 of course started on Logic Circuits. Discussion of area, power and noise margins. |
| Lecture #14 (10/22) | Logic Circuits (Part 4) continued...discussion on rise/fall and propagation delays, fan-in and fan-out and noise margin. |
| MIDTERM (10/24) | |
| Lecture #15 (10/29) | Discussion of midterm problems, Logic circuits (part 4) continued...derivation of noise margins, discussion on resistive-load logic gates. |
| Lecture #16 (10/31) | Reading Text : finish Chap 4. Logic circuits (part 4) continued...discussion on speed, power, area of resistive load circuits. sizing issues for inverters and other logic gates. |
| Lecture #17 (11/07) | Reading Text p446-461. Logic circuits (part 4) continues...Resistive Load Logic circuits finished, complementary load logic started, discussion on noise margins, delay. |
| Lecture #18 (11/12) | complementary load logic continued, discussion on NOR and NAND topologies, Precharged logic gates, pass logic gates covered and introduction to Worst case design approach. |
| Lecture #19 (11/14) | Part 4 of course continued, worst case design : introduction, parameter ranges, examples, worst case corners with examples. Part 5 of the course "Optimization" started...overview of definitions to be used for this. |
| Lecture #20 (11/19) | Part 5 of course continued..., sizing of fixed logic chain, derivation of optimum delay, discussion on interconnect RC delay. |
| Lecture #21 (11/21) | RC interconnects, large fan-in gates, sense amplifier introduction, discussion on charge redistribution amplifiers. |
| Lecture #22 (11/26) | Sense amplifier architectures. Static and clocked differential sense amps, schmidtt trigger, Introduction to adders/datapath. |
| Lecture #23 (11/28) | Arithmatic adders discussed, ripple carry, carry lookahead, carry bypass, carry select |
| Lecture #24 (12/03) | Ref. Chap 9 of tect book, Adders continued, Input protection circuits, output pad drivers. |
| Lecture #25 (12/05) | Domino Logic, precharged logic problem, Multi-level logic. |
| Lecture #26 (12/10) | domino logic contd..., clock drivers, latches, self timed logic. |
| No More Lectures !!! Final exam is on monday, 17th dec'2001 | *** BEST OF LUCK *** |