Abstract

Ultra-wideband Pulse Radio Receiver in Digital CMOS

Ultra-wideband (UWB) systems must coexist in the 3.1-10.6 GHz band 
with a variety of primary, higher power wireless applications, making them 
susceptible to narrowband interferers. This thesis addresses the interference 
challenge at the architectural level through a combination of interference 
detection with agile avoidance, frequency planning and filtering.
A double-conversion receiver architecture is developed based on novel
discrete-time wideband IF correlators that utilize pulse templates pre-stored in
high-speed memories, which allows fast channel switching for agile interferer 
avoidance and requires no phase-locked loop (PLL) resetting.

Design techniques for broadband radio frequency integrated circuits (RFIC)
including distributed low noise amplifier (LNA), active mixers, passive filters and 
gigahertz dividers are described. Design techniques for analog correlators 
including discrete-time multipliers, custom high speed memory circuits, 
multiplexers and switched-capacitor integrators are also described.

An 8-channel 3.1-9.5 GHz UWB pulse radio receiver is realized in a 90 nm
digital CMOS process.  The extensive use of digital circuitry allows the receiver
to have a small area of only 1 mm^2.  The use of true broadband front-end 
circuits allows the receiver to cover both the lower and higher bands of the UWB 
spectrum without external tuning.  The receiver has a high data rate of 50 Mb/s 
using on-off keying (OOK) modulation and a sensitivity of -52 dBm at a BER of 
10^-3. The receiver consumes 130 mA from a 1.2 V supply.

A design methodology for low power MOS distributed LNA is presented and the 
concept of optimal biasing to improve the overall LNA performance is verified 
through a 9 mW DC-7 GHz programmable-gain LNA realized in a 0.18 um 
CMOS process.  The LNA has a flat gain of  8 +/- 0.6 dB, S11 matching of better 
than -16 dB, NF ranging from 4.2-6.2 dB and an IIP3 of +3 dBm.

A study of the eddy current effect of devices placed underneath an on-chip 
inductor is presented.  Layout techniques to minimize eddy current loss and 
unwanted magnetic coupling between devices and the inductor are described.  
Measurement results show that a  compact voltage-controlled oscillator (VCO) 
using the described layout techniques reduces the layout area by 50% while 
exhibiting slightly better phase noise compared to a VCO using a traditional layout.