Ultra-wideband Pulse Radio Receiver
||An 8-channel 3.1-9.5 GHz UWB pulse radio receiver
is realized using a double-conversion architecture with
discrete-time wideband IF correlation. The pulse templates for
correlation are pre-stored in memories which allows fast band
switching and agile interferer avoidance since no PLL resettling
is required. This high
data-rate receiver covers both the lower and higher bands of
the UWB spectrum and avoids the use of tunable bandpass
filters that require manual adjustments for each channel and
occupy a large area. The area of our receiver is small thanks to
the extensive use of high-speed digital circuitry and memories
that will scale in size and performance as technology improves.
F. Zhang, R. Gharpurey and P. Kinget, "A 3.1-9.5 GHz Agile UWB Pulse Radio Receiver with
Discrete-Time Wideband-IF Correlation in 90nm CMOS," IEEE Radio Frequency Integrated
(RFIC), June 2008.
Components and Circuits Underneath Integrated Inductors
|| The idea of utilizing the area under an inductor sprout
from the practical consideration of metal density requirement.
On-chip inductors are large, but they are often made of
only two metal layers. Placing metal fills inside or near the
inductor increases the metal density count but has the possible
drawback of decreasing the Q of the inductor through eddy
current loss. We established
a relationship between fill cell size and inductor Q through extensive
EM simulations and measurements on test structures.
||We used layout techniques to minimize eddy
current loss and magnetic coupling between the devices and the
inductor, and constructed a complete voltage-controlled oscillator
(VCO) inside an inductor. Measurement results show that this
compact VCO has an equal performance in phase noise and
output power as compared to a traditional VCO while reducing
the area by about 50%. The techniques presented in this paper
are general and can be implemented in most layouts without extra
F. Zhang, C.-F. Chu and P. Kinget, "Voltage-controlled
oscillator in the coil," IEEE Custom Integrated Circuits Conference
(CICC), October 2005, pp. 587-590.
F. Zhang and P. Kinget, "Design of Components and Circuits Underneath
Integrated Inductors" IEEE Journal of Solid-State Circuits, pp. 2265-2271,
Oct. 2006. PDF
Low Power Distributed Low Noise Amplifier
||We introduced a design methodology for low power MOS distributed
amplifiers (DAs). The bias point of the MOS
devices is optimized so that the DA can be used as a low-noise
amplifier (LNA) in broadband applications. A prototype 9-mW
LNA with programmable gain was implemented in a 0.18um
CMOS process. The LNA provides a flat gain, S21, of 8 +/- 0.6 dB
from DC to 6.2 GHz, with an input impedance match, S11, of
16 dB and an output impedance match, S22, of 10 dB over
the entire band. The 3-dB bandwidth of the distributed amplifier
is 7 GHz, the IIP3 is +3 dBm, and the noise figure ranges from
4.2 to 6.2 dB. The gain is programmable from 10 dB to +8 dB
while gain flatness and matching are maintained.
- F. Zhang and P. Kinget, "Low Power
Programmable-Gain CMOS Distributed LNA for Ultra-Wideband
Applications," in Digest of Technical Papers IEEE Symposium on VLSI
circuits, June 2005, pp. 78-81.
F. Zhang and P. Kinget, "Low Power Programmable Gain CMOS
Distributed LNA," IEEE Journal of Solid-State Circuits, vol. 41,
no 6, June 2006, pp. 1333-1343.