D. Sitaram, Y. Zheng, and K. L. Shepard, "Full-chip, three-dimensional, shapes-based RLC extraction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May, 2004.
Y. Li, G. Patounakis, K. L. Shepard, and S. M. Nowick, "Design of an asynchronous micropipelined datapath with heterogeneous, dynamic voltage scaling," IEEE Journal of Solid-State Circuits, April, 2004.
G. Patounakis, W. Y. Li, and K. L. Shepard, "A Fully Integrated On-chip DC-DC Conversion and Power Management System," IEEE Journal of Solid-State Circuits, March, 2004.
Y. Zheng and K. L. Shepard, "On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits," IEEE Transactions on VLSI, June, 2003, pp. 336-344.
Steven C. Chan, K. L. Shepard, and Dae-Jin Kim, "Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August, 2002, pages 916-927.
K. L. Shepard and D.-J. Kim, ``Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, July, 2001, pages 888-901.
K. L. Shepard and Z. Tian, ``Return-limited inductance: A practical approach to on-chip inductance extraction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, April, 2000, pages 425-436.
K. L. Shepard, V. Narayanan, and R. Rose, ``Harmony: A methodology for noise analysis in deep submicron digital integrated circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August, 1999, pages 1132 - 1150.
K. Shepard, ``A Headache on Top of a Migraine: The Challenge of SOI," Integrated Systems Design Electronics Journal, December, 1998, pages 14-15.
K. L. Shepard and V. Narayanan, "Conquering noise in deep submicron digital ICs," IEEE Design and Test of Computers, January-March, 1998
K. L. Shepard, S. M Carey, E. K. Cho, B. W. Curran, R. F. Hatch, D. E. Hoffman, S. A. McCabe, G. A. Northrop, and R. Seigler, "Design methodology for the S/390 Parallel Enterprise Server G4 microprocessors," IBM Journal of Research and Development, Volume 41, Number 4/5, pages 515-547, July/September, 1997
C. F. Webb, C. J. Anderson, L. Sigal, K. L. Shepard, J. S. Liptay, J. D. Warnock, B. Curran, B. W. Krumm, M. D. Mayo, P. J. Camporese, E. M. Schwarz, M. S. Farrell, P. J. Restle, R. M. Averill III, T. J. Slegel, W. V. Huott, Y. H. Chan, B. Wile, T. N. Nguyen, P. G. Emma, D. K. Beece, C.-T. Chuang, and C. Price, "A 400-MHz S/390 microprocessor," IEEE Journal of Solid-State Circuits, November, 1997, pages 1665-1675.
K. L. Shepard, M. L. Roukes, and B. P. van der Gaag, "Experimental measurement of scattering coefficients in mesoscopic conductors," Physical Review B 46, 9648 (1992)
K. L. Shepard, M. L. Roukes, and B. P. van der Gaag, "Direct measurment of the transmission matrix of a mesoscopic conductor," Phys. Rev. Lett 68, 2660 (1992)
K. L. Shepard, "Antiscreening and exchange-enhanced spin-splitting in quantum wires," Physical Review B 45, 13431 (1992)
K. L. Shepard, "Disorder and the transition to the quantum Hall regime in quasi-one-dimensional channels," Physical Review B 44, 9088 (1991)
K. L. Shepard, "Multichannel, multiprobe Landauer formula in the presense of a uniform magnetic field," Physical Review B 43, 11623 (1991)
K. Shepard and H. Schumacher, "Scaling in Npn and Pnp heterostructure bipolar transistors," Electronics Letters 24, 111 (1988)
K. Shepard, Z E. Smith, S. Aljishi, and S. Wagner, "Kinetics of the generation and annealing of deep defects and recombination centers in amorphous silicon," Applied Physics Letters 53, 1644 (1988)
Z E. Smith, V. Chu, K. Shepard, S. Aljishi, D. Slobodin, J. Kolodzey, S. Wagner, and T. L. Chu, "Photothermal and photoconductive determination of surface and buld defect densities in amorphous silicon films," Applied Physics Letters 50, 1521 (1987)
S. Rajapandian, Z. Xu, and K. L. Shepard, "Energy-efficient, low-voltage operation of digital CMOS circuits through charge-recycling," Symposium on VLSI Circuits, 2004.
S. C. Chan, P. J. Restle, K. L. Shepard, N. James, and R. Franch, "A 4.8 GHz resonant global clock distribution," Digest of Technical Papers, International Solid-State Circuits Conference, 2004.
S. Rajapandian, Z. Xu, and K. L. Shepard, "Charge-recycling voltage domains for energy-efficient low-voltage operation of digital CMOS circuits," Proceedings of the 2003 International Conference on Computer Design .
S. C. Chan, K. L. Shepard, and P. J. Restle, "Design of resonant global clock distributions," Proceedings of the 2003 International Conference on Computer Design.
Y. Li, G. Patounakis, K. L. Shepard, "High-throughput asynchronous datapath with software-controlled voltage scaling, " VLSI Circuits Symposium, June, 2003.
Y. Li, G. Patounakis, A. Jose, K. L. Shepard and S. M. Nowick, "Asynchronous datapath with software-controlled on-chip adaptive voltage scaling for multirate signal processing applications, " Proceedings of the International Symposium on Asynchronous Circuits and Systems, May, 2003.
Dipak Sitaram, Yu Zheng, and K. L. Shepard, "Implicit treatment of substrate and power-ground losses in return-limited inductance extraction," Proceedings of the International Conference on Computer-Aided Design, 2002.
Steven Chan and K. L. Shepard, ``Practical considerations in RLCK crosstalk analysis for digital integrated circuits," Proceedings of the International Conference on Computer-Aided Design, 2001, pages 598-604.
K. L. Shepard and Yu Zheng, ``On-chip oscilloscopes for noninvasive time-domain measurement of waveforms," Proceedings of the International Conference on Computer Design, September, 2001, pp. 221-226. Best paper award winner
K. L. Shepard, ``CAD Issues for CMOS VLSI Design in SOI," Proceedings of the International Symposium on Quality in Electronic Design, March, 2001, pages 105-110 (invited)
K. L. Shepard, D. Sitaram, and Y. Zheng, ``Full-chip, shapes-based RLC extraction," Proceedings of the International Conference on Computer-Aided Design, November, 2000, pages 142-149.
K. L. Shepard and D.-J. Kim, ``Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology," Proceedings of the Design Automation Conference, June, 2000, pages 239-242.
K. L. Shepard and K. Chou, ``Cell characterization for noise stability," Proceedings of the Custom Integrated Circuits Conference, 2000, pages 91-94.
K. L. Shepard and D.-J. Kim, ``Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis," Proceedings of the International Conference on Computer-Aided Design, 1999, pages 531-538
M. Kamon, S. McCormick, and K. L. Shepard, ``Interconnect Parasitic Extraction in the Digital IC Design Methodology," Proceedings of the International Conference on Computer-Aided Design, 1999, pages 223-230.
K. L. Shepard and Z. Tian, "Return-limited inductances: A Practical Approach to On-Chip Inductance Extraction", Proceedings of the 1999 Custom Integrated Circuits Conference.
K. L. Shepard, "The challenge of high-performance, deep-submicron design in a turnkey ASIC environment", Proceedings of the 1998 International ASIC conference, pp. 183-186. (invited)
K. L. Shepard, "Design methodologies for noise in digital integrated circuits," Proceedings of the Design Automation Conference, 1998.
R. Puri and K. L. Shepard, ``Timing issues in static-dynamic synthesis," ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 1997.
K. L. Shepard, V. Narayanan, P. C. Elmendorf, and Gutuan Zheng, "Global Harmony: Coupled noise analysis for full-chip RC interconnect networks," Proceedings of the International Conference on Computer-Aided Design, 1997, pages 139-146
K. L. Shepard, S. Carey, D. K. Beece, R. Hatch, and G. Northrop, "Design Methodology for the High-Performance G4 3/390 Microprocessor," Proceedings of the International Conference on Computer Design, 1997, pages 232-240
K. L. Shepard, "Practical Issues of Interconnect Analysis in Deep Submicron Integrated Circuits," Proceedings of the International Conference on Computer Design, 1997, pages 532-541
K. L. Shepard and V. Narayanan, "Noise in deep submicron digital design," Proceedings of the International Conference on Computer-Aided Design, 1996, pages 524-531
``Tutorial: Modelling Technology for High Frequency Design ," Design Automation Conference, June, 2002.
``Tutorial: Electrical integrity design and verification for digital and mixed-signal systems-on-a-chip," International Conference on Computer-Aided Design, November, 2001.
``Tutorial: Interconnect-centric electrical integrity verification for systems-on-a-chip," International Conference on Computer-Aided Design, San Jose, November, 2000
`` Noise in CMOS VLSI Chips," Vail Computer Elements Workshop, June, 2000
``Tutorial: Accurate analysis of crosstalk effects in VDSM designs," International Conference on Quality in Electronic Design, San Jose, March 2000.
``Tutorial: Ultra Deep Submicron Design and Analysis," Asian-Pacific Design Automation Conference, Yokohama, Japan, February, 2000
``Panel: How will CAD handle billion-transistor systems?" International Conference on Computer Aided Design, November, 1998.
``Panel: Taming noise in deep submicron digital design," Design Automation Conference, San Francisco, CA, June, 1998
``Tutorial: Analysis/optimization of performance and noise in deep submicron designs," Asian-Pacific Design Automation Conference, Yokohama, Japan, February, 1998
NSF workshop on systems-in-silicon, Princeton University, March, 1998
``Technology and trends for static timing analysis in deep submicron digital integrated circuits," International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Austin, December, 1997 (invited)
``Timing in deep submicron digital design," Computer Elements Workshop, Mesa, Arizona, 1996