Publications

Power management circuits

	S. Rajapandian, Z. Xu, and K. L. Shepard, "Implicit dc-dc downconversion through charge-recycling," Journal of Solid-State Circuit, April, 2005
	S. Rajapandian, K. L. Shepard, P. Hazucha, and T. Karnik, "High-tension power delivery: operating 180-nm CMOS digital logic at a 5.4-V supply," Digest of Technical Papers, International Solid-State Circuits Conference, 2005
	S. Rajapandian, Z. Xu, and K. L. Shepard, "Energy-efficient, low-voltage operation of digital CMOS circuits through charge-recycling," Symposium on VLSI Circuits, 2004.
	S. Rajapandian, Z. Xu, and K. L. Shepard, "Charge-recycling voltage domains for energy-efficient low-voltage operation of digital CMOS circuits," Proceedings of International Conference on Computer Design, 2003.
	G. Patounakis, Y. W. Li, and K. L. Shepard, "A Fully Integrated On-Chip DC-DC Conversion and Power Management System," IEEE Journal of Solid-State Circuits, 2004, March, 2004

Mixed-signal test

	Y. Zheng and K. L. Shepard, "On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits," IEEE Transactions on VLSI, June, 2003, pp. 336-344.
	K. L. Shepard and Yu Zheng, "On-chip oscilloscopes for noninvasive time-domain measurement of waveforms," Proceedings of the International Conference on Computer Design, September, 2001, pp. 221-226. Best paper award winner

Signal integrity CAD

	K. L. Shepard, V. Narayanan, and R. Rose, ``Harmony: A methodology for noise analysis in deep submicron digital integrated circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August, 1999, pages 1132 - 1150.
	K. L. Shepard and V. Narayanan, "Conquering noise in deep submicron digital ICs," IEEE Design and Test of Computers, January-March, 1998.
	K. L. Shepard and D.-J. Kim, ``Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology," Proceedings of the Design Automation Conference, June, 2000, pages 239-242.
	K. L. Shepard and K. Chou, ``Cell characterization for noise stability," Proceedings of the Custom Integrated Circuits Conference, 2000, pages 91-94.
	K. L. Shepard, "Design methodologies for noise in digital integrated circuits," Proceedings of the Design Automation Conference, 1998, pp. 94-99.
	K. L. Shepard, V. Narayanan, P. C. Elmendorf, and Gutuan Zheng, "Global Harmony: Coupled noise analysis for full-chip RC interconnect networks," Proceedings of the International Conference on Computer-Aided Design, 1997, pages 139-146
	K. L. Shepard and V. Narayanan, "Noise in deep submicron digital design," Proceedings of the International Conference on Computer-Aided Design, 1996, pages 524-531

Asynchronous digital signal processing

	Y. Li, G. Patounakis, K. L. Shepard, and S. M. Nowick, "Design of an asynchronous micropipelined datapath with heterogeneous, dynamic voltage scaling," IEEE Journal of Solid-State Circuits, April, 2004
	Y. Li, G. Patounakis, K. L. Shepard, "High-throughput asynchronous datapath with software-controlled voltage scaling," VLSI Circuits Symposium, 2003, pp. 49-52.
	Y. Li, G. Patounakis, A. Jose, K. L. Shepard and S. M. Nowick, "Asynchronous datapath with software-controlled on-chip adaptive voltage scaling for multirate signal processing applications, " Proceedings of the International Symposium on Asynchronous Circuits and Systems, 2003, pp. 216-225.

CAD for SOI

	Steven C. Chan, K. L. Shepard, and Dae-Jin Kim, "Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August, 2002, pages 916-927.
	K. L. Shepard and D.-J. Kim, ``Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, July, 2001, pages 888-901.
	K. L. Shepard, ``CAD Issues for CMOS VLSI Design in SOI," Proceedings of the International Symposium on Quality in Electronic Design, March, 2001, pages 105-110 (invited)
	K. L. Shepard and D.-J. Kim, ``Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis," Proceedings of the International Conference on Computer-Aided Design, 1999, pages 531-538

Inductance extraction and interconnect analysis

	D. Sitaram, Y. Zheng, and K. L. Shepard, ``Full-chip, three-dimensional, shapes-based RLC extraction, IEEE Transactions on CAD, May 2004
	K. L. Shepard and Z. Tian, ``Return-limited inductance: A practical approach to on-chip inductance extraction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, April, 2000, pages 425-436.
	Dipak Sitaram, Yu Zheng, and K. L. Shepard, "Implicit treatment of substrate and power-ground losses in return-limited inductance extraction," Proceedings of the International Conference on Computer-Aided Design, 2002, pp. 94-99.
	Steven Chan and K. L. Shepard, ``Practical considerations in RLCK crosstalk analysis for digital integrated circuits," Proceedings of the International Conference on Computer-Aided Design, 2001, pages 598-604.
	M. Kamon, S. McCormick, and K. L. Shepard, ``Interconnect Parasitic Extraction in the Digital IC Design Methodology," Proceedings of the International Conference on Computer-Aided Design, 1999, pages 223-230.
	K. L. Shepard and Z. Tian, "Return-limited inductances: A Practical Approach to On-Chip Inductance Extraction", Proceedings of the 1999 Custom Integrated Circuits Conference.
	K. L. Shepard, "Practical Issues of Interconnect Analysis in Deep Submicron Integrated Circuits," Proceedings of the International Conference on Computer Design, 1997, pages 532-541

Microprocessor Design and Design Methodology

	C. F. Webb, C. J. Anderson, L. Sigal, K. L. Shepard, J. S. Liptay, J. D. Warnock, B. Curran, B. W. Krumm, M. D. Mayo, P. J. Camporese, E. M. Schwarz, M. S. Farrell, P. J. Restle, R. M. Averill III, T. J. Slegel, W. V. Huott, Y. H. Chan, B. Wile, T. N. Nguyen, P. G. Emma, D. K. Beece, C.-T. Chuang, and C. Price, "A 400-MHz S/390 microprocessor," IEEE Journal of Solid-State Circuits, November, 1997, pages 1665-1675.
	C. F. Webb, C. J. Anderson, L. Sigal, K. L. Shepard, J. S. Liptay, J. D. Warnock, B. Curran, B. W. Krumm, M. D. Mayo, P. J. Camporese, E. M. Schwarz, M .S. Farrell, P. J. Restle, R. M. Averill, III, T. J. Slegel, W. V. Huott, Y. H. Chan, B. Wile, and P. Emma, "A 400MHz S/390 Microprocessor," Proceedings of the International Solid-State Circuits Conference, 1997, pages 168-169.
	K. L. Shepard, S. Carey, D. K. Beece, R. Hatch, and G. Northrop, "Design Methodology for the High-Performance G4 3/390 Microprocessor," Proceedings of the International Conference on Computer Design, 1997, pages 232-240
	K. L. Shepard, "The challenge of high-performance, deep-submicron design in a turnkey ASIC environment," Proceedings of the 1998 International ASIC conference, pp. 183-186. (invited)

Resonant clock distributions

	S. C. Chan, K. L. Shepard, and P. J. Restle, "1.1-1.6 GHz distributed differential oscillator global clock network," Digest of Technical Papers, International Solid-State Circuits Conference, 2005.
	S. C. Chan, K. L. Shepard, and P. J. Restle, "Uniform-phase, uniform-amplitude resonant-load global clock distribution," Journal of Solid-State Circuits, January, 2005
	S. C. Chan, P. J. Restle, K. L. Shepard, N. James, and R. Franch, "A 4.8 GHz Resonant Global Clock Distribution," Digest of Technical Papers, International Solid-State Circuits Conference, 2004.
	S. C. Chan, K. L. Shepard, and P. J. Restle, "Design of resonant global clock distributions," Proceedings of International Conference on Computer Design, 2003.

Biomolecular sensors

G. Patounakis, K. L. Shepard, and R. Levicky, "Active CMOS biochip for time-solved fluorescence detection," Symposium on VLSI Circuits, 2005 (to appear)

Intrachip communications circuits

A. P. Jose, G. Patounakis, and K. L. Shepard, "Near speed-of-light on-chip interconnects using pulsed current-mode signalling," Symposium on VLSI Circuits, 2005 (to appear)