Read This Document Before InstallationTable of Contents1.0. Introduction 2.0. Installation 3.0. Known Issues
3.2. Synthesis 3.3. Implementation 3.4. Timing Simulation 3.5. Documentation Back to Top |
1.0. IntroductionThank you for purchasing the LogiCORE PCI64 interface from Xilinx! The Xilinx LogiCORE PCI64 interface provides you with a fully pre-verified, pre-implemented, 64-bit PCI initiator and target interface for Virtex devices. This detailed and well documented design can save you months of engineering time.This release note supports Version 3.0 of the LogiCORE PCI64 Interface. The following devices are supported in all releases:
If you have purchased the Virtex product, the following designs are
also supported:
1.1. ContentsThe contents of the LogiCORE PCI64 interface are listed in the following sections. All customers are entitled to download the design files using the web based configuration and download tool. Customers who have purchased a design kit option will also receive the design kit hardware and software under separate cover.1.2. SoftwareThe full set of downloadable files from the web based configuration and download tool is listed below. Note that some files may not appear in your download, depending on the download options you select when running the download tool.(installation directory)
For more details on the LogiCORE PCI64 interface, see the following documents included in the docs/ sub-directory of your download.
1.3. MaintenanceThis product comes with one year of maintenance from the original purchase date; you are entitled to receive major product and documentation updates during that time.1.4. SupportThis product comes with free technical and product information telephone support (toll free in the U.S. and Canada). You can also fax or email your questions.The fastest method for obtaining LogiCORE PCI64 interface technical support is through the support.xilinx.com web page. Your inquiry is routed to a team of engineers with specific expertise in using the LogiCORE PCI64 interface. Xilinx provides technical support for use of the LogiCORE PCI64 interface product as described in the LogiCORE PCI Design Guide and the LogiCORE PCI Implementation Guide. Xilinx cannot guarantee timing, functionality, or support of the LogiCORE PCI64 interface product if designs are implemented in unsupported devices or if the product is customized beyond what is allowed in the LogiCORE PCI Design Guide. Back to Top |
2.0. InstallationThis section explains the system requirements and how to install the LogiCORE PCI64 interface after downloading it from the web based configuration and download tool.2.1. System RequirementsIn order to use the LogiCORE PCI64 interface, you must verify that your computing platform is capable of running the required design tools. Consult the documentation shipped with your design tools to verify that your computing platform is sufficient.The LogiCORE PCI64 interface requires the use of either Xilinx Alliance Xilinx Foundation tools, version 6.1i Service Pack 1. Various third party synthesis and simulation tools are supported. These may be selected "a la carte" from the list below: Verilog Design Flow:
2.2. Unpacking FilesDuring configuration and download, a selection is made between ZIP format and GZ format for the download. The contents of the ZIP file and the GZ file are identical.If you have downloaded the customPciCore.zip file, then you can use any unzip utility to decompress and extract the files. Suitable tools include "unzip" on UNIX workstations, and "winzip" on Microsoft Windows platforms. If you have downloaded the customPciCore.tar.gz file, you must first decompress the file using the GNU "gunzip" utility. After decompressing the file, extract the files from the TAR archive using the command "tar xvf customPciCore.tar". These utilities are readily available on UNIX workstations. For ease of use, users of Microsoft Windows should download the ZIP file instead of the GZ format file. Make a cursory comparison of the resulting directories and files to the list presented in the Software section to make sure you received the files you expected. Back to Top |
3.0. Known IssuesThis is a list of known issues. Please read this entire section so that you are aware of any late breaking information.3.1. Functional SimulationNone.3.2. SynthesisNone.3.3. ImplementationThe design files present in this release are based on timing parameters from, and intended for use with, the speedfiles shipped with the supported tools. As more device characterization data is collected, Xilinx may update the speedfiles to more closely model device operation.Xilinx reserves the right to modify the design files, including the PCI interface pinout, in order to maintain full PCI compliance after speedfile updates occur. To the full extent possible, Xilinx will incorporate such modifications without using pinout changes in an effort to provide "transparent" design file updates. For some 66 MHz designs, bitgen must be run with a special option to change the behavior of a global clock buffer used in the design. When you are ready to generate a bitstream for a 66 MHz design, run bitgen with the following option:
This option must not be used for Virtex-II designs. This option must not be used for 33 MHz designs. Various warnings may be issued by the Xilinx tools. However, no errors should occur. The UCF files for some Virtex-II implementations may have pin placement constraints which use preferred global clock input pins for non-clock PCI signals. For some applications, this can be problematic if these special pin locations could be better used for clock inputs. If this applies to your application, you may re-assign the location of these pins in the UCF file. For applications where the user has implemented MSI capability in the user configuration space, please note that this interface does not support the assertion of SERR# by the user application. SERR# assertion is used to signal MSI writes that have been abnormally terminated. 3.4. Timing SimulationIn all designs, timing violations may be reported during timing simulation. This behavior is expected for two reasons. First, this interface uses address stepping which can result in intermediate or unknown data to be present on the bus during clock edges. Second, the timing specifications used during place and route are very specific to eliminate false timing paths; however, the simulation tool does not know which paths are false and must report timing violations on all paths.3.5. DocumentationIf you have downloaded the reduced fileset, Spartan-II only version of this interface, please note that the examples in the Implementation Guide use a device which is not available in this download. Please note that you will need to follow the directions to target a device that is available in this download; this includes changing the synthesis target and modifying the Xilinx implementation scripts to select an available part and package combination.Back to Top |
4.0. Customer SupportFor registration, authorization codes, update information, warranty status, shipping, product issues, and technical support, call Monday through Friday, 8 a.m. to 5 p.m. Pacific time.4.1. RegistrationYou must be a registered customer to access the web based configuration and download tool. If you have questions regarding your registration status, or forget your password, you may contact Xilinx Customer Service for assistance:
4.2. Technical SupportTechnical support may be reached by the following means:
4.3. TrainingThe Xilinx Training Administrator may be contacted at 1-408-879-5090. International customers should contact a local sales representative or distributor.Back to Top |