**********************Computer Hardware Design**********************

**********************Professor Ken Shepard*************************

**********************Multiplier Design****************************

**********************Prepared by Victoria Wang********************


**********************INPUT AND OUTPUT INTO THE DATAPATH*************

--Create Entity:
--Library=EE4340,Cell=mult_data,View=entity
--Time:Fri Feb 27 18:42:37 2004
--By:vluluw

LIBRARY ieee;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_1164.all;
ENTITY mult_data IS
    PORT(
        isZero : OUT std_ulogic;
        q0 : OUT std_ulogic;
        sa : IN std_ulogic_vector(1 DOWNTO 0);
        sq : IN std_ulogic_vector(1 DOWNTO 0);
        sc : IN std_ulogic_vector(1 DOWNTO 0);
        sb : IN std_ulogic;
        scar : IN std_ulogic;
        data_in : IN std_ulogic_vector(15 DOWNTO 0);
        clock : IN std_ulogic;
        reset : IN std_ulogic;
        mout : OUT std_ulogic_vector(31 DOWNTO 0)
    );
END mult_data;


********************BEHAVIOR OF DATAPATH************************

architecture behavior of mult_data is

signal countmux : std_ulogic_vector(3 downto 0):= "0000";
signal bmux, amux, qmux: std_ulogic_vector(15 downto 0):= "0000000000000000";
signal cmux: std_ulogic := '0';
signal cout: std_ulogic:='0';
signal countout : std_ulogic_vector(3 downto 0) := "0000";
signal bout, aout, qout : std_ulogic_vector(15 downto 0):= "0000000000000000";
signal shift_inA, shift_inQ : std_ulogic_vector (15 downto 0) := "0000000000000000";
signal sum : std_ulogic_vector (16 downto 0) := "00000000000000000";
signal temp : std_ulogic_vector (3 downto 0) := "0000";

begin

with sc select         
	countmux <= "1111" when "00",
		temp when "01",
		countout when "11",
		"XXXX" when others;

with sb select
	bmux <= data_in when '0',
		bout when '1',
		"XXXXXXXXXXXXXXXX" when others;

with sa select 
	amux <= "0000000000000000" when "00",
		sum(15 downto 0) when "01",
		shift_inA when "10",
		aout when "11",
		"XXXXXXXXXXXXXXXX" when others;

with sq select 
	qmux <= data_in when "00",
		shift_inQ when "01",
		qout when "11",
		"XXXXXXXXXXXXXXXX" when others;

with scar select
	cmux <= '0' when '0',
		sum(16) when '1',
		'X' when others;

temp <= to_stdulogicvector(unsigned(countout) - '1');

isZero <= not(countout(3) OR  countout(2) OR countout(1) OR countout(0));


shift_inA <= '0'& aout(15 downto 1);
shift_inQ <= aout(0)&qout(15 downto 1);

sum <= to_stdulogicvector(unsigned('0'&bout)+unsigned(aout));

mout <= aout&bout; 

regP: process(clock,reset)
begin
	if reset = '1' then 
	countout <= "0000";
	elsif (clock = '1' and clock'event) then
	countout <= countmux;
	end if;
end process;

regB: process(clock, reset)
begin
	if reset = '1' then
	bout <= "0000000000000000";
	elsif (clock = '1' and clock'event) then 
	bout <= bmux;
	end if;
end process;

regC: process(clock,reset)
begin
        if reset = '1' then
        cout <= '0';
        elsif (clock = '1' and clock'event) then
        cout <= cmux;
	end if; 
end process;

regA: process(clock, reset) 
begin	
        if reset = '1' then
        aout <= "0000000000000000"; 
        elsif (clock = '1' and clock'event) then
        aout <= amux;
	end if;
end process;

q0 <= qout(0);

regQ: process(clock, reset) 
begin
        if reset = '1' then
        qout <= "0000000000000000"; 
        elsif (clock = '1' and clock'event) then
        qout <= qmux;
	end if;
end process;
end;