Handouts :
| #1 | Syllabus | |
| #2 | Problem Set 1 (due 2/4) | |
| #3 | Amdahl paper on IBM S/360 | |
| #4 | VHDL examples | |
| #5 | Problem Set 2 (due 2/18) | |
| #5a | Problem Set 2 Solutions | datapath controller |
| #6 | Lab 1 (due 3/3) | |
| #7 | PDP/8 Design Handout 1 (Fetch controls) | |
| #8 | Practice midterm | |
| #9 | Lab 2 (due 3/24) | |
| #10 | PCI Overview handout | |
| #10 | Lab 3A (due 3/31) | |
| #11 | Lab 3B (due 3/31) | |
| #12 | Lab 4A (due 4/12) | |
| #13 | Lab 4B (due 4/12) | |
| #14 | Lab 5B (due 4/19) | |
| #15 | Final project report and presentation guidelines for PDP/8 project |
These
documents will also be available in paper form in a binder in Mudd 1211.
Please do not remove these from the lab. Also note that because many of
these documents are confidential or proprietary, access is limited to those in
the cisl.columbia.edu or ee.columbia.edu domains.
| #1 | PCI-DDR Board Schematics | |
| #2 | Board stack-up and fabrication instructions | |
| #3 | Top layer board layout plot | |
| #4 | Bottom layer board layout plot | |
| #5 | Xilinx data sheets (we are using part XC2V1000-5FG456) | |
| #6 | DDR S-DRAM datasheet (we are using part MT46V16M16) | |
| #7 | Configuration PROM datasheet (we are using XCF04S-VO20) | |
| #8 | PCI Core Implementation Guide | |
| #9 | PCI Core Design Guide | |
| #10 | PCI Core Release Notes | html |
| #11 | PCI Local Bus Specification | |
| #12 | Xilinx DDR controller reference design | |
| #13 | Jungo Windriver manual | |
| #14 | Jungo Windriver quick-start guide | |
| #15 | PCI PING64 reference design |