This schedule is tentative and subject to change.
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Topics |
Readings | |
| Lecture 1 | Review of MOS design physics and CMOS scaling trends
BSIM device models, emerging technology issues affecting circuits (e. g. subthreshold and gate leakage) |
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| Lecture 2 | Static CMOS
Sizing for speed, review of method of logical effort |
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| Lecture 3,4 | Interconnect analysis
RC and RLC on-chip interconnect analysis. Explicit moment-matching techniques. Implicit moment-matching techniques based on Krylov-subspace model-order reduction. |
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| Lecture 5 | Other non-clocked logic styles
Differential static CMOS style (i. e. DCVS) Current-mode logic Pass transistor logic |
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| Lecture 6 | Clocked storage elements: latches and flip-flops
pass-transistor and tri-state inverter latch TSPC latches sense-amplifier based latches |
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| Lecture 7 | Clocked logic families
Domino, delay-reset domino Self-resetting domino |
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| Lecture 8 | Clocking styles, single phase and multiphase clocking styles
with clocked and unclocked logic families. Cycle stealing | |
| Lecture 9 | Self-timed design with clocked and non-clocked logic. Asynchronous
pipelines. |
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| Lecture 10,11 | Low-power design techniques
"optimal" energy-delay product as a function of Vdd/Vth on-chip voltage regulation and well biasing use of multi-Vts for leakage reduction clock gating adiabatic logic |
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| Midterm (3/13) | ||
| Lecture 12 | Design considerations for SOI technology. |
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| Lecture 13 | SRAM design
self-resetting SRAM design techniques, wave-pipelining sense amps, replica bit lines |
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| Lecture 14 | DRAM design |
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| Lecture 15 | Power supply
distribution. Low-skew clock distribution techniques: clock trees and grids. |
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| Lecture 16,17 | PLL/DLL design. Basic building blocks: phase detector, charge pump, delay lines, VCO. | |
| Lecture 18 | Introduction to Verilog A | |
| Lecture 19 | I/O circuitry
Low-voltage interface standards (e. g. SSTL and GTL) ESD protection Driver and receiver design |