EE6930-ADVANCED DIGITAL INTEGRATED CIRCUITS : Online course reader

EE E6930 - ADVANCED DIGITAL INTEGRATED CIRCUITS

Online course reader

This course reader is under construction and will be continuously augmented as the semester progresses.

These are selected journal and conference papers (in PDF format) that will be useful references. Most of these papers are IEEE copyrighted. As such, they should only be used for personal, classroom use.

Advanced CMOS Technology Issues

S. Borkar, "Design challenges of technology scaling," IEEE Micro, July-August, 1999, pp. 23-29.(PDF)
B. Davari et al., "CMOS scaling for high performance and low power - the next ten years," Proceedings of the IEEE, April, 1995.(PDF)

Interconnect analysis

Elmore delay

Jorge Rubinstein, Paul Penfield, Jr., and Mark Horowitz, "Signal Delay in RC Tree Networks," IEEE Transactions on Computer-Aided Design, July, 1983, pp. 202-211 (PDF)

Explicit moment matching

L. T. Pillage and R. A. Rohrer, "Asymptotic Waveform Evaluation for Timing Analysis," IEEE Transactions on Computer-Aided Design, April, 1990, pp. 352-366.(PDF)
Peter R. O'Brien and Thomas Savarino, "Efficient on-chip delay estimation for leaky models of multiple-source nets," Proceedings of the Custom Integrated Circuits Conference, 1990, pp. 9.6.1-9.6.4. (PDF)

Implicit moment matching

P. Feldman and R. W. Freund, "Efficient linear circuit analysis by Pade approximation via the Lanczos process," IEEE Transactions on Computer-Aided Design, May, 1995, pp. 639-649.(PDF)
A. Odabasioglu, M. Celik, and L. Pileggi. "PRIMA: Passive reduced-order interconnect macromodelling algorithm," IEEE Transactions on Computer-Aided Design, August, 1998, pp. 645-654. (PDF)

Non-clocked logic

Overview

V. Oklobdzija, "Differential and pass-transistor CMOS logic for high performance systems," Proceedings of the 21st International Conference on Microelectronics, Volume 2, 1997, pp. 803-810. (PDF)

DCVS

L. G. Heller, et al, "Cascode voltage witch logic: a differential CMOS logic family," Proceedings of the 1984 IEEE Solid-State Circuits Confererence, pp. 16-17.(PDF)

Pass-transistor logic

K. Yano, et al, "A 3.8-ns CMOS 16x16-b multiplier using complementary pass-transistor logic," IEEE Journal of Solid-State Circuits, April, 1990, pp. 388-395.(PDF)
K. Yano et al, "Top-down pass-transistor logic design," IEEE Journal of Solid-State Circuits, June, 1996, pp. 792-803.(PDF)
M. Suzuki, et al, "A 1.5 ns 32-b CMOS ALU in double pass-transistor logic," IEEE Journal of Solid-State CIrcuits, November, 1993, pp. 1145-1151.(PDF)

Current-mode logic

J. M. Musicer and J. Rabaey, "MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environment," Proceedings of the ISLPED, 2000, pp. 102-107. (PDF)

Clocked storage elements

Most of these papers actually describe microprocessor designs, but the latches are an important part of the design.

TSPC latches

D. Dobberpuhl, R. Witek, et. al, "A 200-MHz 64-b dual-issue CMOS Microprocessor," IEEE Journal of Solid-State Circuits, November 1992, pp. 1585-1598.(PDF)

Sense-amplifier latches

J. Montanaro, R. Witek, et al, "A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor," IEEE Journal of Solid-State Circuits, November, 1996, pp. 1703-1714. (PDF)

Pulsed-clock latches

H. Partovi, R. Burd, et al., "Flow-through latch and edge-triggered flip-flop hybrid elements," 1996 ISSCC Digest of Technical Papers, pp. 138-139.(PDF)
C. F. Webb, C. J. Anderson, L. Siegel, K. Shepard, et al, "A 400-MHz S/390 Microprocessor," IEEE Journal of Solid-State Circuits, November, 1997, pp. 1665-1675.(PDF)

Asynchronous and self-timed design

S. Schuster, et al, "Interlocked pipelined CMOS," 2000 International Solid-State Circuits Conference (PDF)

Low-power design

Overview

A. P. Chandrakasan and R. W. Broderson, "Minimizing power consumption in digital CMOS circuits," Proceedings of the IEEE, April, 1995, pp. 498-523. (PDF)
J. D. Meindl, "Low power microelectronics: retrospect and prospect," Proceedings of the IEEE, Paril, 1995, pp. 619-635. (PDF)

Adaptive body bias

T. Kuroda, et al, "A 0.9-V, 150-MHz, 10-mW, 4 mm², 2-D discrete cosine transform core processor with variable threshold-voltage (Vt) scheme," IEEE Journal of Solid-State Circuits, November, 1996, pp. 1770-1779. (PDF)
J. S. Witters, G. Groeseneken, and H. W. Maes, "Analysis and modelling of on-chip high-voltage geenrator circuits for use in EEPROM circuits," IEEE Journal of Solid-State Circuits, October, 1989, pp. 1372-1380. (PDF)

Adiabatic logic

L. J. Svensson and J. G. Koller, "Driving a capacitive load without dissipating fCV²," 1994 IEEE Symposium on Lower Power Electronics, pp. 100-101. (PDF).
Y. Moon and D.-K. Jeong, "An efficient charge recovery logic circuit," IEEE Journal of Solid-State Circuits, April, 1996, pp. 514-522 (PDF).
W. C. Athas, et al, "Low-power digital systems based on adiabatic-switching principles," IEEE Transactions on VLSI, December, 1994, pp. 398-407.(PDF)

DC-DC converter design

A. J. Stratakos, S. R. Sanders, and R. W. Broderson, "A low-voltage CMOS DC-DC converter for a portable battery-operated system," IEEE Power Electronics Specialists Conference, June, 1994, pp. 619-626. (PDF)

SOI

Ching-Te Chuang, Pong-Fei Lu, and Carl J. Anderson, "SOI For Digital CMOS VLSI: Design Considerations and Advances," Proceedings of the IEEE, April, 1998, pp. 689 - 720 (PDF)
A. G. Aipperspach, D. H. Allen, D. T. Cox, H. V. Phan, and S. N. Storino, "A 0.2-um, 1.8-V, SOI, 500-MHZ, 64-b PowerPC microprocessor with copper interconnects," IEEE Journal of Solid-State Circuits, November, 1999, pp. 1430-1435. (PDF)
K. L. Shepard and D.-J. Kim, "Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis," IEEE Transactions on Computer-Aided Design on Integrated Circuits and Systems, July, 2001, pp. 888-901. (PDF)

Power distribution

Howard Chen and D. D. Ling, "Power supply noise analysis methodology for deep-submicron VLSI chip design," Proceedings of the 37th Design Automation Conference, pp. 638-642, June, 1997 (PDF)
A. Dharchoudhury, R. Panda, D. Blaauw, and R. Vaidyanathan, "Design and analysis of power distribution networks in PowerPC microprocessors," Proceedings of the 38th Design Automation Conference, pp. 738-743, June, 1998 (PDF)
G. Steele, D. Overhauser, S. Rochel, S. Z. Hussain, "Full-chip verification methods for DSM power distribution systems," Proceedings of the 38th Design Automation Conference, pp. 744-749, June, 1998. (PDF)

Clock distribution

Conventional trees and grids

Daniel W. Bailey and Bradley J. Benschneider, "Clocking Design and Analysis for a 600-MHz Alpha Microprocessor," IEEE Journal of Solid-State Circuits, November, 1998, pp. 1627 - 1633 (PDF)
Phillip J. Restle, et al, "A Clock Distribution Network for Microprocessors," IEEE Journal of Solid-State Circuits, May, 2001, pp. 792 - 799 (PDF)

Distributed PLLs and multiple PLLs

Gill A. Pratt and John Nguyen, "Distributed Synchronous Clocking," IEEE Transactions on Parallel and Distributed Systems, March, 1995, pp. 314 - 328 (PDF)

Vadim Gutnik and Anantha P. Chandrakasan, "Active GHz Clock Network Using Distributed PLLs," IEEE Journal of Solid-State Circuits, November, 2000, pp. 1553-1559. (PDF)

H. Mizuno and K. Ishibashi, "A Noise-Immune GHz-Clock Distribution Scheme using Synchronous Distributed Oscillators," Digest of Technical Papers, International Solid-State Circuits Conference, 1998, pp. 404-405. (PDF)

PLL/DLL Design

John G. Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits, November, 1996, pp. 1723 - 1732. (PDF)
P. Larsson, "High-speed architecture for a programmable frequency divider and a dual-modulus prescalar," IEEE Journal of Solid-State Circuits, November, 1996, pp. 744-748. (PDF)
Stefanos Sidiropoulos, Dean Liu, Jeaha Kim, Guyeon Wei, and Mark Horowitz, "Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers, Symposium on VLSI Circuit Digest of Technical Papers, 2000, pp. 124-127. (PDF)
Stefanos Sidiropoulous and M. A. Horowitz, "A Semidigital Dual Delay-Locked Loop," IEEE Journal of Solid-State Circuits, November, 1997, pp. 1683-1692. (PDF)

Memory Design

SRAM

T. Chappell, et al, "A 2-ns Cycle, 3.8-ns Access 512-Kb CMOS ECL SRAM with a Fully Pipelined Architecture," IEEE Journal of Solid-State Circuits, November, 1991, pp. 1577-1585 (PDF)
T. Hirose et al, "A 20nS 4Mb CMOS SRAM with Hierarchical Word Decoding Architecture," IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 1990, pp. 132-133 (PDF)
K. Sasaki et al, "A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier," IEEE Journal of Solid-State Circuits, November, 1992, pp. 1511-1517 (PDF)

DRAM

T. Takahashi, et al, "A multigigabit DRAM technology with 6F² open-bitline cell, distributed overdriven sensing, and stacked-flash fuse," IEEE Journal of Solid-State Circuits, November, 2001, pp. 1721-1727. (PDF)
Asakura, et al, "An experimental 256-Mb DRAM with boosted sense-ground scheme," IEEE Journal of Solid-State Circuits, November, 1994, pp. 1303-1309. (PDF)
K. Itoh, "Trends in megabit DRAM circuit design," IEEE Journal of Solid-State Circuits, June, 1990, pp. 778-789. (PDF)
T. Kirihata, et al, "A 390-mm², 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture," IEEE Journal of Solid-State Circuits, November, 1999, pp. 1580-1588 (PDF)

Verilog-A/Verilog-AMS

Peter Frey and Donald O'Riordan, "Verilog-AMS: Mixed-Signal Simulation and Cross Domain Connect Modules" (PDF)

ESD Issues

C. Ito, K. Banerjee, and R. W. Dutton, "Analysis and design of ESD protection circuits for high-frequency/RF applications," International Symposium on Quality Electronic Design, 2001. (PDF)
M.-D. Ker, T.-Y. Chen, C.-Y. Wu, and H.-H. Chang, "ESD protection design on analog pin with very low input capacitance for high-frequency or currrent-mode applications," IEEE Journal of Solid-State Circuits, August 2000. (PDF)
J. E. Vinson and J. J. Liou, "Electrostatic discharge in semiconductor devices: protection techniques," Proceedings of the IEEE, December, 2000. (PDF)
C. Duvvury, S. Ramaswamy, A. Amerasekera, R. A. Cline, R. H. Andresen, and V. Gupta, "Substrate pump NMOS for ESD protection applications," EOS/ESD Symposium 2000. (PDF)
S. Ramaswamy, C. Duvvury, A. Amerasekera, V. Reddy, and S. M. Kang, "EOS/ESD analysis of high-density logic chips," EOS/ESD Symposium 1996. (PDF)
C. Duvvury, "ESD protection device issues of IC designs," Custom Integrated Circuits Conference, 2001. (PDF)
C. Duvvury and D. Dias, "Dynamic gate coupling of NMOS for efficient output ESD protection," International Reliability Physics Symposium, 1992. (PDF)
A. Amerasekera, C. Duvvury, V. Reddy, and M. Rodder, "Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes," International Electron Device Meeting, 1995. (PDF)
W. R. Anderson and D. B. Krakauer, "ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration," EOS/ESD Symposium, 1998. (PDF)
J. Z. Chen, A. Amerasekera, and C. Duvvury, "Design methodology for optimizing gate driven ESD protection circuits in submicron CMOS processes," EOS/ESD Symposium, 1997. (PDF)

High-speed links

C. K. Yang, M. Horowitz, "A 0.8-um CMOS 2.5Gb/s oversampling receiver and transmitter for serial links," IEEE Journal of Solid-State Circuits, December, 1996, pp. 2015-2023. (PDF)
C. K. Yang, R. Farjad-Rad, M. Horowitz, "A 0.5-um CMOS 4.0 Gbps transceiver with data recovery using oversampling," IEEE Journal of Solid-State Circuit, May, 1998, pp. 713-722. (PDF)
M.-J. E. Lee, W. Dally, and P. Chiang, "Low-power area-efficient high-speed I/O circuit techniques," IEEE Journal of Solid-State Circuits, November, 2000, pp. 1591-1599. (PDF)

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