How-to for layout-dependent device models, pcells, and Virtuoso-XL

This how-to is under construction and will be periodically updated, so check back.

Traditionally, custom layout has been done with "polygon pushing" which can be an extremely tedious and time-consuming process. Fortunately, modern industrial CAD tools for layout try to "automate" some of the process by using predefined layouts for the devices (pcells), which are parameterized and by maintaining connectivity information, which helps in wiring up these devices in the layout.

At the same time, it is important that your schematic reflect, as accurately as possible, your post-layout extracted results. In particular, we want to correctly model the source-drain diffusion capacitances, which can represent a significant fraction of the device capacitance. To accomplish this, we have devised a comprehensive set of device parameters which you must specify on each device in the schematic. These parameters are used to automatically calculate the AS, AD, PS, and PD parameters for SPICE and are used to generate the pcell instances for you in layout in Virtuoso-XL.

When you instantiate a device in your schematic, you need to do so with the following parameters (which will appear on the component instantiation form when the component is created):

• Width. The transistor width.
• Length. The transistor length. The default is 0.24 um (the minimum length).
• Number of fingers. This specifies the number of fingers used for a multifinger device. The width you specify with the "width" parameter will be the total effective width.
• Layout type. There are 16 options here: cc, ce, cn, cs, ec, ee, en, es, nc, ne, nn, ns, sc, se, sn, and ss. These allow you to specify the nature of the diffusions on the "left" side and "right" side of the device (gate running vertical). (It would be better if I drew some picture here, but I'm lazy.) The diffusions are labelled alternating source-drain, beginning with source on the left. A "c" diffusion indicates a full contact, defining the edge of the active region. A "n" diffusion indicates no contact with presumed sharing with the contact of another device (an "e" device). A "s" diffusion indicates no contact with presumed sharing to an "n" device. A "e" diffusion indicates a full contact but with presumed sharing with another device.

Once you have a schematic with all the parameters appropriately specified for the devices, you can start to generate your layout with Virtuoso-XL. From the layout window, choose Tools -> Design Synthesis -> Layout XL. On the ``Virtuoso XL Startup Option" window, choose "Create New" and OK the form. "OK" the "Create New File" form to create a layout. Now, we can automatically instantiate the pcells from the schematic with appropriate connectivity. From the layout editor window, choose Design -> Gen from source. Choose the layers for the pins for the design and "prBoundary drawing" for the PR boundary of the layout. "OK" the form. You should get a layout with the pcells instantiated, with placements approximately given by the placements in the schematics. To see the connectivity, choose Options -> Display. In the "Display Options" form, select "Nets" for display. This will give you flight lines for wiring up your schematic. Selecting devices and pins in the layout causes the corresponding devices in the schematic to be highlighted (cross-probing). Because the connectivity is also know, you can perform simple connectivity checking before running LVS. More details can be found in "openbook" in the Virtuoso-XL documentation.