EE E4332: VLSI Design Lab

In this course, the students are designing a MP3 decoder chip, including both the hardware and software design. The chip will be fabricated in a 0.25 um, 5-level metal process from TSMC.

Important announcements

Our design reviews are scheduled for Friday, March 3 from 10 AM - 12:30 PM and on Sunday, March 5 from 5 - 7:30 PM in the Interschool Lab on the 7th floor of CEPSR. A detailed group schedule will be sent by e-mail.

General information

Course handouts

Syllabus (Postscript)(PDF)
Group assignments (Postscript)(PDF)
Tools Tutorial #1. VHDL design entry and simulation (Postscript)(PDF)
Tools Tutorial #2. Design Compiler (Postscript)(PDF)
Design review guidelines. (Postscript)(PDF)
Tools Tutorial #3. Dracula DRC/LVS (Postscript)(PDF)
How-to on layout-dependent device models, pcells, and Virtuoso-XL
How-to on abstract generation
IRSIM how-to (Postscript)(PDF)
Pearl how-to

Group handouts

MAC group work items (Postscript)(PDF)
ALU/shifter group work items (Postscript)(PDF)
I-unit group work items (Postscript)(PDF)
Software group work items (Postscript)(PDF)
SRAM group work items (Postscript)(PDF)
Memory/host interface group work items (Postscript)(PDF)
Analog group work items (Postscript)(PDF)

Project specifications and working documents

ALU/shifter group

Design review (PDF)

DAC group

Design review (PDF)

Memory/host-interface group

Design review (Postscript)

Iunit group

Design review for decode (PDF)

Final design documentation

SRAM group
I-unit group: instruction decode
MAC group
I-unit group: Program control
DAC group
Software group
SMC/EPP interface

Product datasheets

ADSP-2100 Family User's Manual
32M x 8 Bit SmartMedia Card (PDF)
128K x 8 bit Uniform Sector Flash Memory (PDF)

Other reference material

EPP parallel-port protocol

Ken Shepard - shepard@ee.columbia.edu