Glenn Cowan
Sanjeev Ranganathan
Jiang-Tao Yi
The samples come to the DAC at rates near 44kHz while the blocks downstream operate at 64 times this. To avoid unwanted out of band energy the signal must be filtered. This is done in steps. The first three blocks each upsample by two and perform low pass filtering. The fourth block upsamples by eight and performs linear interpolation on the samples. The first three blocks are implemented using a two phase structure shown below. The output multiplexer selects between the two paths at twice the rate of the rest of the system. Each "f12" block is an FIR with symmetrical impulse response. The order of the first filter is 92 while the second and third are 8 and 5 respectively.
Second Order Multi-Bit Modulator
Delta-Sigma modulators are used to trade off an increased requirement of digital signal processing to high performance analog blocks. The single bit modulator discussed in the design review does decrease the requirement of the dac to a single bit, but the requirements on the post dac filtering to reduce the out of band noise is very large. In order to alleviate the requirement a multi-bit modulator was used.
The architecture of the multi-bit modulator is shown in below. It uses 17-level Master DAC the output of which contains the information of the input signal. One look at the modulator reveals that the input has a feed forward path to the the quantizer and the modulator only processes the quantization error. A large dither signal generated by a 32-bit LSR with amplitude +/- 1/2 LSB is added to linearize the quantizer.
The output of the Master modulator is shown in figure for an input sine wave. There is a lot of noise out of band as seen by the large glitches in the output. In order to reduce the out of band noise some auxillary DACs are used. The first auxillary filter is a first order modulator that takes the input from the integrated error signal of the first modulator (which is again marginally dithered to avoid any tonal behavior) and converts it into a three bit signal which after differentiation becomes another scaled 17-level representation of the quantization noise.
The error generated by this stage is split bit wise and taken by 5 scaled sigle bit DACs which after differentiation become a 3-levels each.
The scaling in the auxillary DACs is not obvious from the block diagram. Each of the auxillary DACs are scaled with respect to the master. (This is achieved by scaling the stepsize in the block diagram). This scaling is to be achieved by the analog circuits to follow. The scaling was required to be 0.5 for the first auxillary DAC and 1/2, 1/4, 1/8, 1/16 and 1/32 for the one bit DAC with respect to the reference of the master DAC.
The final output is shown below
This analysis assumes that the individual multi-bit DACs are completely linear. Any mismatch here will directly reflect in the output. This linearization is achieved by local mismatch shaping in each DAC.
Current Steering DAC
The modulator is independent of the circuit implementation of the DAC. The switch capacitor implementations of the post filters were shown in the design review. However, due to the modulator architecture, the out of band noise is very small and no further filtering is required.
As the analog circuit sits in a hostile high frequency digital circuit and no deep well isolation is possible, the substrate coupled noise could potentially get amplified by the switch capacitor circuit.
To avoid these problems, the DAC was a continuous time current steering DAC. The output current is driven through feedback resistors in the amplifier.
The current source is a dual return to zero type of current source that eliminates inter-symbol interference. The current sources are cascoded to give it high output impedance. The switching is based on the clock and is independent of the signal.
The layout of the current sources is shown below.
The idea of Mismatching shaping is to use each of the thermometer-coded current sources equally so that the accumulation of error would be a minum if we consider the average of the current sources as the reference current. Mathematically, if the accumulation error is boundary (white) noise, the spectrum of mismatching noise is shaped to high frequency ( out of signal band).
input sequence .....................0 ..0 ...1 ..0 ..2 .1 ..0 ..2 ..2 ..1.. 1 ..1 ..1 ..0.. 1 ..2 ....
3 level thermo ouput ............00 00 10 01 11 10 11 11 11 01 10 01 10 00 01 11....
from this data sample , we can see the two current sources for thermo output are swithed on and off nearly equally, |n1-n2|<=1, and the accumulation error is less than |I1-I2|/2.
But the noise spectrum may have the tone from the alternating of 01 and 10. To eliminate the tone, we should switch on either of the current source randomly when they have been switched on equal times. This is called a dithered scrambler.
The following shows how dithered and nondeithered scramblers work.
The amplifier features a class A-B translinear, common source output stage. Below are some of its key features.
| Input Transconductance | 1mS |
| Output Transconductance | 30mS |
| DC Gain into 330Ohms | 40000 |
| Unity Gain Frequency into 300Ohms
in series with 32Ohms||200pF |
20MHz |
| Quiescent output current | 2mA |
| THD for 1V peak into 330Ohms | 100dB |
| Input referred noise | 7.5nV/HZ^0.5 |
Inside the symbol "opamp_o_p_stage" are the actual output devices. The pfet is 900by0.5um and the nfet is 200by0.5um