In this course, students work in teams to design a complete VLSI chip which is fabricated by MOSIS in an HP 0.6um process

The VLSI CAD Lab in Mudd 1212 will be open Monday through Friday from 3 - 6 PM.

General information

Course handouts

• Syllabus (PS) (PDF) (HTML)
• Project Suggestions (PS) (PDF)
• Preliminary Project Proposal (PS) (PDF)
• VHDL Examples (PS) (PDF)
• Design Flow (PS) (PDF)
• Design Review (PS) (PDF)
• MOSIS Scalable CMOS (SCMOS) Design Rules (Revision 7.2)  (PDF)
• Tutorial 1 (PS) (PDF)
• Chapter 2-5, Page 27-205, composer tutorial (PS) (PDF)
• Tutorial 2 (PS) (PDF)
• Tutorial 3 (PS) (PDF)
• Tutorial 4 (PS) (PDF)

Homeworks

• Homework #1 (PS) (PDF)
• Homework #2 (PS) (PDF)

Class Newsgroup (columbia.spring.elen4332)

Projects

Several groups may want to consider entering their designs in the Student VLSI Design Contest

Instructor: Ken Shepard shepard@ee.columbia.edu